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git01.mediatek.com / filogic / uboot / 7c767adb003ad18b096ad61e323cfeeb88b85db2 / drivers / clk / clk_stm32mp1.c
  1. 80cb568 stm32mp1: clk: support digital bypass by Patrick Delaunay · 6 years ago
  2. 201f0d5 stm32mp1: clk: add ADC clock gating by Patrick Delaunay · 6 years ago
  3. effe2b4 stm32mp1: clk: update Ethernet clock gating by Patrick Delaunay · 6 years ago
  4. 8314d2c stm32mp1: clk: add LDTC and DSI clock support by Patrick Delaunay · 6 years ago
  5. 5327d37 stm32mp1: clk: add common function pll_get_fvco by Patrick Delaunay · 6 years ago
  6. a7c0fd6 stm32mp1: clk: define RCC_PLLNCFGR2_SHIFT macro by Patrick Delaunay · 6 years ago
  7. b139a5b misc: stm32: Add STM32MP1 support by Patrick Delaunay · 6 years ago
  8. 4cb3b53 clk: stm32mp1: Add VREF clock gating by Fabrice Gasnier · 7 years ago
  9. 8b0c8a1 SPDX: Convert all of our multiple license tags to Linux Kernel style by Tom Rini · 7 years ago
  10. bf7d944 clock: stm32mp1: add stgen clock source change support by Patrick Delaunay · 7 years ago
  11. f11398e clk: stm32mp1: add clock tree initialization by Patrick Delaunay · 7 years ago
  12. e6ab627 clk: add driver for stm32mp1 by Patrick Delaunay · 7 years ago