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git01.mediatek.com / filogic / uboot / 7376b52ffe76f82c8b88cdffde6913100f700e74 / drivers / clk / mediatek / clk-mtk.c
  1. 94fc842 clk: mediatek: use unsigned type for returning the clk rate by Fabien Parent · Thu Oct 17 21:02:05 2019 +0200
  2. 65da8e7 clk: mediatek: fix clock-rate overflow problem by developer · Fri Jan 10 16:30:30 2020 +0800
  3. 0b5e5f1 clk: mediatek: add configurable pcw_chg_reg/ibits/fmin to mtk_pll by developer · Tue Dec 31 11:29:22 2019 +0800
  4. ba560c7 clk: mediatek: add set_clr_upd mux type flow by developer · Tue Dec 31 11:29:21 2019 +0800
  5. 69463e5 clk: mediatek: add support for SETCLR_INV and NO_SETCLR flags by Fabien Parent · Sun Mar 24 16:46:35 2019 +0100
  6. 2186c98 clk: MediaTek: add clock driver for MT7629 SoC. by developer · Thu Nov 15 10:07:54 2018 +0800