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git01.mediatek.com / filogic / uboot / 72c622e5ce8607540425fe13f68114bcaedd3f08 / drivers / clk / clk_versal.c
  1. 98697a1 clk: versal: Remove alt_ref_clk from clock sources by Rajan Vaja · Mon May 04 22:53:56 2020 -0700
  2. 6b9f010 common: Drop asm/ptrace.h from common header by Simon Glass · Sun May 10 11:40:06 2020 -0600
  3. 0f2af88 common: Drop log.h from common header by Simon Glass · Sun May 10 11:40:05 2020 -0600
  4. 274e0b0 common: Drop net.h from common header by Simon Glass · Sun May 10 11:39:56 2020 -0600
  5. aa12d51 clk: versal: Fix watchdog clock issue by T Karthik Reddy · Wed Apr 08 21:34:54 2020 -0600
  6. 5986efc versal: drivers: clk: Fix invalid clock name queries by Rajan Vaja · Thu Jan 16 03:55:05 2020 -0800
  7. 9bc1564 dm: core: Create a new header file for 'compat' features by Simon Glass · Mon Feb 03 07:36:16 2020 -0700
  8. d66c5f7 dm: core: Require users of devres to include the header by Simon Glass · Mon Feb 03 07:36:15 2020 -0700
  9. 142fb5b arm64: versal: Rename versal_pm_request to xilinx_pm_request by Michal Simek · Fri Oct 04 15:52:43 2019 +0200
  10. e50c104 arm64: versal: Clean pm_api_id usage by Michal Simek · Fri Oct 04 15:25:18 2019 +0200
  11. f7a7120 clk: versal: Add clock driver support by Siva Durga Prasad Paladugu · Sun Jun 23 12:24:57 2019 +0530