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git01.mediatek.com / filogic / uboot / 71fa5b4a77cb90573917e7104a8f79247c171f3b / drivers / ddr / altera / sdram_soc64.c
  1. 71fa5b4 dm: treewide: Rename 'platdata' variables to just 'plat' by Simon Glass · Thu Dec 03 16:55:18 2020 -0700
  2. 8a2b47f dm: treewide: Rename auto_alloc_size members to be shorter by Simon Glass · Thu Dec 03 16:55:17 2020 -0700
  3. f7ed78b treewide: convert bd_t to struct bd_info by coccinelle by Masahiro Yamada · Fri Jun 26 15:13:33 2020 +0900
  4. 0f2af88 common: Drop log.h from common header by Simon Glass · Sun May 10 11:40:05 2020 -0600
  5. 9758973 common: Drop init.h from common header by Simon Glass · Sun May 10 11:40:02 2020 -0600
  6. 274e0b0 common: Drop net.h from common header by Simon Glass · Sun May 10 11:39:56 2020 -0600
  7. 9bc1564 dm: core: Create a new header file for 'compat' features by Simon Glass · Mon Feb 03 07:36:16 2020 -0700
  8. f11478f common: Move hang() to the same header as panic() by Simon Glass · Sat Dec 28 10:45:07 2019 -0700
  9. 4ddb909 ddr: altera: agilex: Add SDRAM driver for Agilex by Ley Foon Tan · Wed Nov 27 15:55:27 2019 +0800
  10. 25572cf ddr: altera: Restructure Stratix 10 SDRAM driver by Ley Foon Tan · Wed Nov 27 15:55:26 2019 +0800