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git01.mediatek.com / filogic / uboot / 6f71881d9df74925b14310cb51caab8bcc4e4e5c / cpu / mpc8xxx / ddr / main.c
  1. 9dbbd7b Coding style cleanup, update CHANGELOG by Wolfgang Denk · Sat Sep 13 02:23:05 2008 +0200
  2. 124b082 FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code. by Kumar Gala · Tue Aug 26 15:01:29 2008 -0500