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git01.mediatek.com / filogic / uboot / 6e33dea400803edf543ea6300c9fe2acb3fcf1a2 / board / freescale / imx8mp_evk / lpddr4_timing.c
  1. c67140d Merge tag 'u-boot-imx-20210409' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx by Tom Rini · Fri Apr 09 07:41:32 2021 -0400
  2. 2207afa5 imx8m: ddr: Disable CA VREF Training for LPDDR4 by Ye Li · Fri Mar 19 15:57:14 2021 +0800
  3. 6292783 imx8mp: refine power on imx8mp board by haidong.zheng · Fri Mar 19 15:57:02 2021 +0800
  4. 225f45e imx8mp_evk: Update LPDDR4 refresh time by Ye Li · Fri Mar 19 15:57:01 2021 +0800
  5. 4facb0c imx8mp_evk: Update LPDDR4 timing for new FW 202006 by Ye Li · Fri Mar 19 15:57:00 2021 +0800
  6. 5ffb1f7 imx8mp: ddr: Add inline ECC feature support by Sherry Sun · Fri Mar 19 15:56:59 2021 +0800
  7. c83e7f9 imx8mp: Disables use of MR4 TUF flag (MR4[7]) bit by Jian Li · Thu Feb 27 09:40:10 2020 +0800
  8. 742b1eb imx8mp: DDR performance tunning by Jian Li · Mon Jan 20 15:14:42 2020 +0800
  9. 6f27594 imx8mp: enable rd_port_urgent by Jian Li · Wed Jan 08 10:14:16 2020 +0800
  10. c47e09d imx: add i.MX8MP EVK board by Peng Fan · Mon Dec 30 17:46:21 2019 +0800