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git01.mediatek.com / filogic / uboot / 6d24073c9df60ed77bb3c390d178acebabf02afe / drivers / fpga / zynqpl.c
  1. 94dc92f fpga: zynqpl: Do not place bitstream below 1MB by Michal Simek · Fri Oct 04 10:48:59 2013 +0200
  2. 8cfb246 fpga: zynqpl: Add dcache flush support by Jagannadha Sutradharudu Teki · Fri Sep 20 18:39:47 2013 +0530
  3. bd8ec7e Coding Style cleanup: remove trailing white space by Wolfgang Denk · Mon Oct 07 13:07:26 2013 +0200
  4. 5577585 fpga: zynqpl: Clear loopback mode during device init by Soren Brinkmann · Fri Jun 14 17:43:24 2013 -0700
  5. 52f91b5 fpga: zynqpl: Add support for zc7100 device. by Michal Simek · Mon Jun 17 13:54:07 2013 +0200
  6. d79de1d Add GPL-2.0+ SPDX-License-Identifier to source files by Wolfgang Denk · Mon Jul 08 09:37:19 2013 +0200
  7. 15d654c fpga: zynq: Add support for loading bitstream by Michal Simek · Mon Apr 22 15:43:02 2013 +0200