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git01.mediatek.com / filogic / uboot / 6d0d99151654d106e316f2abfc49ef5f8a215519 / board / altera / cyclone5-socdk / qts / pll_config.h
  1. 10e4779 SPDX: Convert all of our single license tags to Linux Kernel style by Tom Rini · Sun May 06 17:58:06 2018 -0400
  2. d28f4a7 arm: socfpga: Update iomux and pll for c5 socdk RevE by Dinh Nguyen · Tue May 10 15:13:59 2016 -0500
  3. 418db66 arm: socfpga: Fix QSPI doesn't work on socdk board by shengjiangwu · Tue Dec 22 17:18:09 2015 +0800
  4. c213f63 arm: socfpga: Fix emac1 doesn't work on socdk board by shengjiangwu · Tue Dec 22 15:22:02 2015 +0800
  5. 372f70d arm: socfpga: Switch to filtered QTS files by Marek Vasut · Mon Aug 10 21:21:07 2015 +0200
  6. 3f4c561 arm: socfpga: Split Altera socfpga into AV and CV SoCDK by Marek Vasut · Mon Aug 10 21:24:53 2015 +0200[Copied from board/altera/socfpga/qts/pll_config.h]
  7. 20a0739 arm: socfpga: Move generated files into qts subdir by Marek Vasut · Sat Jul 25 08:22:21 2015 +0200[Renamed from board/altera/socfpga/pll_config.h]
  8. b1194c2 arm: socfpga: spl: update peripheral pll for dev kit by Dinh Nguyen · Wed Apr 15 16:44:33 2015 -0500
  9. 3debe33 arm: socfpga: Sync Cyclone V DK PLL configuration by Marek Vasut · Tue Dec 30 19:41:17 2014 +0100
  10. 43dca1e arm: socfpga: clock: Add missing stubs into board file by Marek Vasut · Sat Sep 13 08:16:49 2014 +0200
  11. cb35060 socfpga: Adding Clock Manager driver by Chin Liang See · Tue Mar 04 22:13:53 2014 -0600