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git01.mediatek.com / filogic / uboot / 65b5be2a20d3483aeacd2d277b3b0ffb6619061c / arch / powerpc / cpu / mpc8xxx / ddr / main.c
  1. 80ad401 8xxx/ddr: add support to only compute the ddr sdram size by Haiying Wang · Wed Dec 01 10:35:31 2010 -0500
  2. 2d8ecac MPC8xxx DDR: align informational prints by Becky Bruce · Fri Dec 17 17:17:59 2010 -0600
  3. 93799ca powerpc/8xxx: Fix bug in memctrl interleaving & bank interleaving on cs0~cs4 by york · Fri Jul 02 22:25:52 2010 +0000
  4. 88fbf93 Move arch/ppc to arch/powerpc by Stefan Roese · Thu Apr 15 16:07:28 2010 +0200[Renamed from arch/ppc/cpu/mpc8xxx/ddr/main.c]
  5. 29514c7 ppc: Move cpu/$CPU to arch/ppc/cpu/$CPU by Peter Tyser · Mon Apr 12 22:28:09 2010 -0500[Renamed from cpu/mpc8xxx/ddr/main.c]
  6. f4018f9 85xx, 86xx: Add common board_add_ram_info() by Peter Tyser · Fri Jul 17 10:14:48 2009 -0500
  7. 68ef4bd fsl-ddr: Fix handling of >4G of memory when !CONFIG_PHYS_64BIT by Kumar Gala · Thu Jun 11 23:42:35 2009 -0500
  8. 45eea1d fsl-ddr: Allow system to boot if we have more than 4G of memory by Kumar Gala · Tue Feb 10 23:53:40 2009 -0600
  9. b135d93 fsl ddr skip interleaving if not supported. by Ed Swarthout · Wed Oct 29 09:21:44 2008 -0500
  10. b834f92 Check DDR interleaving mode by Haiying Wang · Fri Oct 03 12:37:10 2008 -0400
  11. fa44036 Pass dimm parameters to populate populate controller options by Haiying Wang · Fri Oct 03 12:36:55 2008 -0400
  12. 272b596 Make DDR interleaving mode work correctly by Haiying Wang · Fri Oct 03 12:36:39 2008 -0400
  13. 9dbbd7b Coding style cleanup, update CHANGELOG by Wolfgang Denk · Sat Sep 13 02:23:05 2008 +0200
  14. 124b082 FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code. by Kumar Gala · Tue Aug 26 15:01:29 2008 -0500