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git01.mediatek.com / filogic / uboot / 64042099e61a8aa14cfd3ce3d9c91301d2d65d5d / arch / powerpc / cpu / mpc8xxx / ddr / options.c
  1. 6404209 powerpc/8xxx: Enabled hwconfig for memory interleaving by Kumar Gala · Wed Jul 14 10:04:21 2010 -0500
  2. 88fbf93 Move arch/ppc to arch/powerpc by Stefan Roese · Thu Apr 15 16:07:28 2010 +0200[Renamed from arch/ppc/cpu/mpc8xxx/ddr/options.c]
  3. 29514c7 ppc: Move cpu/$CPU to arch/ppc/cpu/$CPU by Peter Tyser · Mon Apr 12 22:28:09 2010 -0500[Renamed from cpu/mpc8xxx/ddr/options.c]
  4. 707aa5c fsl-ddr: change the default burst mode for DDR3 by Dave Liu · Fri Mar 05 12:22:00 2010 +0800
  5. 64ee7df fsl-ddr: add the override for write leveling by Dave Liu · Wed Dec 16 10:24:37 2009 -0600
  6. 0f9318f fsl-ddr: Fix the chip-select interleaving issue by Dave Liu · Thu Nov 12 07:26:37 2009 +0800
  7. 4be87b2 fsl-ddr: add the DDR3 SPD infrastructure by Dave Liu · Sat Mar 14 12:48:30 2009 +0800
  8. c0f3b3c fsl-ddr: ignore memctl_intlv_ctl setting if only one DDR controller by Kumar Gala · Fri Feb 06 09:56:34 2009 -0600
  9. a06d74c fsl-ddr: use the 1T timing as default configuration by Dave Liu · Fri Nov 21 16:31:43 2008 +0800
  10. b135d93 fsl ddr skip interleaving if not supported. by Ed Swarthout · Wed Oct 29 09:21:44 2008 -0500
  11. b834f92 Check DDR interleaving mode by Haiying Wang · Fri Oct 03 12:37:10 2008 -0400
  12. fa44036 Pass dimm parameters to populate populate controller options by Haiying Wang · Fri Oct 03 12:36:55 2008 -0400
  13. 124b082 FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code. by Kumar Gala · Tue Aug 26 15:01:29 2008 -0500