1. d911168 mvebu: axp: Rename MV_DDR_32BIT to CONFIG_DDR_32BIT by Phil Sutter · 9 years ago
  2. 33aa8de axp: Fix debugging support in DDR3 write leveling by Phil Sutter · 9 years ago
  3. ff7ad17 arm: mvebu: Make ECC support configurable on Armada XP by Stefan Roese · 9 years ago
  4. 3c6b6fc arm: mvebu: ddr: Fix compilation warning by Stefan Roese · 9 years ago
  5. dea4e33 arm: mvebu: Fix SAR1_CPU_CORE_MASK by Dirk Eibach · 9 years ago
  6. 0277a6b arm: mvebu: a38x: Remove unsupported topologies by Kevin Smith · 9 years ago
  7. 69bab55 bitops: introduce BIT() definition by Heiko Schocher · 9 years ago
  8. f3345e6 arm: mvebu: Add complete SDRAM ECC scrubbing by Stefan Roese · 9 years ago
  9. e4a0f27 arm: mvebu: sdram: Enable ECC support on Armada XP by Stefan Roese · 9 years ago
  10. 61cee0a arm: mvebu: a38x: Use correct PEX register access macros by Stefan Roese · 9 years ago
  11. 5ffceb8 arm: mvebu: Add Armada 38x DDR3 training code from Marvell bin_hdr by Stefan Roese · 10 years ago
  12. eb753e9 arm: mvebu: drivers/ddr: Move Armada XP DDR init code into new directory by Stefan Roese · 10 years ago