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git01.mediatek.com / filogic / uboot / 6330dfec1eee1ce38a0a4c50b8890d9f1ea754cc / arch / riscv / cpu / cpu.c
  1. 6134659 riscv: add run mode configuration for SPL by Lukas Auer · Wed Aug 21 21:14:43 2019 +0200
  2. f942636 riscv: Access CSRs using CSR numbers by Bin Meng · Wed Jul 10 23:43:13 2019 -0700
  3. 3043b90 riscv: prior_stage_fdt_address should only be used when OF_PRIOR_STAGE is enabled by Rick Chen · Tue Apr 30 13:49:35 2019 +0800
  4. e5e6c36 riscv: Introduce CONFIG_XIP to support booting from flash by Rick Chen · Tue Apr 30 13:49:33 2019 +0800
  5. a359665 riscv: add support for multi-hart systems by Lukas Auer · Sun Mar 17 19:28:37 2019 +0100
  6. a7544ed riscv: Do some basic architecture level cpu initialization by Bin Meng · Wed Dec 12 06:12:40 2018 -0800
  7. edfe9a9 riscv: Update supports_extension() to use desc from cpu driver by Bin Meng · Wed Dec 12 06:12:38 2018 -0800
  8. 2caa1ee riscv: Remove non-DM version of print_cpuinfo() by Bin Meng · Wed Dec 12 06:12:35 2018 -0800
  9. 7a3bbfb riscv: Probe cpus during boot by Bin Meng · Wed Dec 12 06:12:34 2018 -0800
  10. 39a652b riscv: save hart ID and device tree passed by prior boot stage by Lukas Auer · Thu Nov 22 11:26:29 2018 +0100
  11. 055700e riscv: Add a helper routine to print CPU information by Bin Meng · Wed Sep 26 06:55:14 2018 -0700