- 54bcf26 riscv: fu540: Use correct API to get L2 cache controller base address by Bin Meng · 4 years, 3 months ago
- 03de50e riscv: sifive: fu540: redundant initialization by Heinrich Schuchardt · 4 years, 4 months ago
- 6b15551 riscv: sifive/fu540: kconfig: Move FU540 driver related options to the SoC level by Bin Meng · 4 years, 4 months ago
- 2b2d9c4 riscv: sifive/fu540: spl: Rename soc_spl_init() by Bin Meng · 4 years, 4 months ago
- 4e3ba2a riscv: Fix linking error when building u-boot-spl with no SMP support by Leo Yu-Chi Liang · 4 years, 5 months ago
- e70ef90 env: Enable SPI flash env for SiFive FU540 by Jagan Teki · 4 years, 5 months ago
- 257875d riscv: Make SiFive HiFive Unleashed board boot again by Bin Meng · 4 years, 4 months ago
- 90fa4e9 Merge branch 'next' by Tom Rini · 4 years, 5 months ago
- 8a52128 riscv: sifive: fu540: enable all cache ways from U-Boot proper by Pragnesh Patel · 4 years, 6 months ago
- 7f4b666 riscv: Add option to support RISC-V privileged spec 1.9 by Sean Anderson · 4 years, 5 months ago
- b1d0cb3 riscv: Clean up IPI initialization code by Sean Anderson · 4 years, 5 months ago
- 84df2e1 riscv: Clear pending interrupts before enabling IPIs by Sean Anderson · 4 years, 5 months ago
- e00653c riscv: sifive: fu540: add SPL configuration by Pragnesh Patel · 4 years, 6 months ago
- 25269c0 riscv: cpu: fu540: Add support for cpu fu540 by Pragnesh Patel · 4 years, 6 months ago
- 45b4ad9d riscv: Add _image_binary_end for SPL by Pragnesh Patel · 4 years, 6 months ago
- 4dcacfc common: Drop linux/bitops.h from common header by Simon Glass · 4 years, 7 months ago
- 9758973 common: Drop init.h from common header by Simon Glass · 4 years, 7 months ago
- 274e0b0 common: Drop net.h from common header by Simon Glass · 4 years, 7 months ago
- 111b804 riscv: Provide a mechanism to fix DT for reserved memory by Atish Patra · 4 years, 7 months ago
- b161f90 riscv: Introduce SPL_SMP Kconfig option for U-Boot SPL by Bin Meng · 4 years, 8 months ago
- 88fc2a5 riscv: Merge unnecessary SMP ifdefs in start.S by Bin Meng · 4 years, 8 months ago
- 6c1e6dd riscv: qemu: Remove the simple-bus driver for the SoC node by Bin Meng · 4 years, 8 months ago
- d12b55b riscv: ax25: cache: Remove SPL_RISCV_MMODE config check by Pragnesh Patel · 4 years, 9 months ago
- 750fee5 riscv: Remove unnecessary instruction by Sean Anderson · 4 years, 10 months ago
- e8b46a1 riscv: Add option to print registers on exception by Sean Anderson · 5 years ago
- 5e75a27 riscv: Fix breakage caused by linker relaxation by Sean Anderson · 5 years ago
- 284f71b common: Move relocate_code() to init.h by Simon Glass · 5 years ago
- c308e01 riscv: add option to wait for ack from secondary harts in smp functions by Lukas Auer · 5 years ago
- 55bc1bd riscv: Fix clear bss loop in the start-up code by Rick Chen · 5 years ago
- 883275d riscv: ax25: cache: Add SPL_RISCV_MMODE for SPL by Rick Chen · 5 years ago
- 276292a riscv: ax25: add SPL support by Rick Chen · 5 years ago
- 6980b6b common: Move board_get_usable_ram_top() out of common.h by Simon Glass · 5 years ago
- 8f3f761 common: Move enable/disable_interrupts out of common.h by Simon Glass · 5 years ago
- 6333448 common: Move ARM cache operations out of common.h by Simon Glass · 5 years ago
- 1d91ba7 common: Move some cache and MMU functions out of common.h by Simon Glass · 5 years ago
- 49cb706 riscv: cache: use CCTL to flush d-cache by Rick Chen · 5 years ago
- 05a684e riscv: cache: Flush L2 cache before jump to linux by Rick Chen · 5 years ago
- 19117d2 riscv: ax25: add imply v5l2 cache controller by Rick Chen · 5 years ago
- b9ad45d riscv: update fix_rela_dyn by Marcus Comstedt · 5 years ago
- 2a2a925 riscv: support SPL stack and global data relocation by Lukas Auer · 5 years ago
- 396f0bd riscv: add SPL support by Lukas Auer · 5 years ago
- 6134659 riscv: add run mode configuration for SPL by Lukas Auer · 5 years ago
- f942636 riscv: Access CSRs using CSR numbers by Bin Meng · 5 years ago
- 43ec7e0 CONFIG_SPL_SYS_[DI]CACHE_OFF: add by Trevor Woerner · 6 years ago
- 3043b90 riscv: prior_stage_fdt_address should only be used when OF_PRIOR_STAGE is enabled by Rick Chen · 6 years ago
- e5e6c36 riscv: Introduce CONFIG_XIP to support booting from flash by Rick Chen · 6 years ago
- f71410a riscv: ax25: Andes specific cache shall only support in M-mode by Rick Chen · 6 years ago
- 14a1075 riscv: ax25: Add platform-specific Kconfig options by Rick Chen · 6 years ago
- cddde09 riscv: hang if relocation of secondary harts fails by Lukas Auer · 6 years ago
- 9ebf294 riscv: do not rely on hart ID passed by previous boot stage by Lukas Auer · 6 years ago
- a359665 riscv: add support for multi-hart systems by Lukas Auer · 6 years ago
- 8de4b3e riscv: save hart ID in register tp instead of s0 by Lukas Auer · 6 years ago
- 01558e2 riscv: delay initialization of caches and debug UART by Lukas Auer · 6 years ago
- 0bbe9cf riscv: generic: Ensure that U-Boot runs within 4GB for 64bit systems by Anup Patel · 6 years ago
- 1240cd6 riscv: Rename cpu/qemu to cpu/generic by Anup Patel · 6 years ago
- 6280e32 riscv: move the AX25-specific implementation of flush_dcache_all by Lukas Auer · 6 years ago
- 89681a7 riscv: Save boot hart id to the global data by Bin Meng · 6 years ago
- 1f46f6d riscv: Return to previous privilege level after trap handling by Bin Meng · 6 years ago
- ea95452 riscv: Fix context restore before returning from trap handler by Bin Meng · 6 years ago
- 2e128a7 riscv: Move trap handler codes to mtrap.S by Bin Meng · 6 years ago
- a7544ed riscv: Do some basic architecture level cpu initialization by Bin Meng · 6 years ago
- edfe9a9 riscv: Update supports_extension() to use desc from cpu driver by Bin Meng · 6 years ago
- 2caa1ee riscv: Remove non-DM version of print_cpuinfo() by Bin Meng · 6 years ago
- 7a3bbfb riscv: Probe cpus during boot by Bin Meng · 6 years ago
- 8fa4478 riscv: qemu: Add platform-specific Kconfig options by Bin Meng · 6 years ago
- 4b284ad riscv: ax25: Hide the ax25-specific Kconfig option by Bin Meng · 6 years ago
- 66c6935 riscv: qemu: Create a simple-bus driver for the soc node by Bin Meng · 6 years ago
- 2a21815 riscv: ax25-ae350: Pass dtb address to u-boot with a1 register by Rick Chen · 6 years ago
- 89b3934 riscv: Add kconfig option to run U-Boot in S-mode by Anup Patel · 6 years ago
- 842d580 riscv: cache: Implement i/dcache [status, enable, disable] by Rick Chen · 6 years ago
- 39a652b riscv: save hart ID and device tree passed by prior boot stage by Lukas Auer · 6 years ago
- 8598e6b riscv: do not blindly modify the mstatus CSR by Lukas Auer · 6 years ago
- 230ab8a riscv: remove unused labels in start.S by Lukas Auer · 6 years ago
- ccd035a Drop CONFIG_INIT_CRITICAL by Bin Meng · 6 years ago
- af51285 riscv: align mtvec on a 4-byte boundary by Lukas Auer · 6 years ago
- 7cf4368 riscv: fix inconsistent use of spaces and tabs in start.S by Lukas Auer · 6 years ago
- de8d80e riscv: Move do_reset() to a common place by Bin Meng · 6 years ago
- 8a8694d riscv: Add QEMU virt board support by Bin Meng · 6 years ago
- bcb3843 riscv: Make start.S available for all targets by Bin Meng · 6 years ago
- 055700e riscv: Add a helper routine to print CPU information by Bin Meng · 6 years ago
- c7feb19 riscv: Fix coding style issues in the linker script by Bin Meng · 6 years ago
- a28e0f5 riscv: Move the linker script to the CPU root directory by Bin Meng · 6 years ago
- b28f7b3 riscv: Include bss subsections in linker script by Alexander Graf · 6 years ago
- 94a10f2 efi_loader: Rename sections to allow for implicit data by Alexander Graf · 6 years ago
- b66af37 riscv: cpu: nx25: Rename as ax25 by Rick Chen · 7 years ago
- 9677a37 efi_loader: Enable RISC-V support by Rick Chen · 7 years ago
- 10e4779 SPDX: Convert all of our single license tags to Linux Kernel style by Tom Rini · 7 years ago
- 40a6fe7 riscv: ae250: Support DT provided by the board at runtime by Rick Chen · 7 years ago
- e76b804 riscv: cpu: Add nx25 to support RISC-V by Rick Chen · 7 years ago