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git01.mediatek.com / filogic / uboot / 5c3767e34fa8e765b736b242d64b1ef4fa80dc22 / arch / arm / mach-socfpga / board.c
  1. 8fdb419 ARM: socfpga: Reorder Arria10 SPL by Marek Vasut · Sat Aug 18 19:11:52 2018 +0200
  2. 911a665 ARM: socfpga: Assure correct CPACR configuration by Marek Vasut · Thu Jul 12 15:07:46 2018 +0200
  3. 27f05ac arm: socfpga: Fix: Compile MCR instruction on ARM 32-bit only by Ley Foon Tan · Thu Jul 12 19:13:34 2018 +0800
  4. 72cc958 ARM: socfpga: Assure correct ACTLR configuration by Marek Vasut · Tue May 29 16:16:46 2018 +0200
  5. f3f525c ARM: socfpga: Adding SoCFPGA info for both SPL and U-Boot by Tien Fong Chee · Tue Dec 05 15:58:08 2017 +0800
  6. a5bfce3 ARM: socfpga: Adding clock frequency info for U-Boot by Tien Fong Chee · Tue Dec 05 15:58:07 2017 +0800
  7. 3710de7 ARM: socfpga: Add DRAM bank size initialization function by Tien Fong Chee · Tue Dec 05 15:58:01 2017 +0800
  8. 10e4779 SPDX: Convert all of our single license tags to Linux Kernel style by Tom Rini · Sun May 06 17:58:06 2018 -0400
  9. 05204f6 arm: socfpga: Introduce common board code by Marek Vasut · Sat Dec 05 21:07:23 2015 +0100