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git01.mediatek.com / filogic / uboot / 5c1bb517cb0b3b310103595ddd1af00f1f447d0f / cpu / mpc8xxx / ddr / ctrl_regs.c
  1. 5c1bb51 fsl-ddr: update the bit mask for DDR3 controller by Dave Liu · 16 years ago
  2. d90e040 Add debug information for DDR controller registers by Haiying Wang · 16 years ago
  3. 272b596 Make DDR interleaving mode work correctly by Haiying Wang · 16 years ago
  4. 35ad58d Fix compiler warning in mpc8xxx ddr code by Kumar Gala · 16 years ago
  5. 124b082 FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code. by Kumar Gala · 16 years ago