Log - 5c02a1ffc4c783afcee6f6f340b1447139748d95 - filogic/uboot

532543c ARM: tegra: add APIs the clock uclass driver will need by Stephen Warren · Tue Sep 13 10:45:56 2016 -0600
1453d10 ARM: tegra: add peripheral clock init table by Stephen Warren · Tue Sep 13 10:45:55 2016 -0600
e237880 Add more SPDX-License-Identifier tags by Tom Rini · Thu Jan 14 22:05:13 2016 -0500
0cab3ec Various Makefiles: Add SPDX-License-Identifier tags by Tom Rini · Tue Nov 10 01:06:16 2015 +0000
0fca329 ARM: tegra114: Clear IDDQ when enabling PLLC by Thierry Reding · Tue Sep 08 11:38:04 2015 +0200
4c3aaa7 ARM: tegra: clk_m is the architected timer source clock by Thierry Reding · Thu Aug 20 11:42:20 2015 +0200
366b24f of: clean up OF_CONTROL ifdef conditionals by Masahiro Yamada · Wed Aug 12 07:31:55 2015 +0900
a8480ef Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc. by Tom Warren · Thu Jun 25 09:50:44 2015 -0700
f069960 arch: Make board selection choices optional by Joe Hershberger · Tue May 12 14:46:23 2015 -0500
ed1632a ARM: tegra: collect SoC sources into mach-tegra by Masahiro Yamada · Fri Feb 20 17:04:04 2015 +0900