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git01.mediatek.com / filogic / uboot / 5ab7ef085f782679dd682d88d0cbd5bc34f46393 / drivers / clk / renesas / clk-rcar-gen3.c
  1. 5ab7ef0 clk: renesas: Tear clock controller down last before booting OS by Marek Vasut · Sat Apr 25 14:57:55 2020 +0200
  2. ba2c7d2 clk: renesas: Update R-Car Gen3 driver Gen4 support by Marek Vasut · Tue Feb 28 22:34:38 2023 +0100
  3. f5e6084 Merge branch 'master' into next by Tom Rini · Mon Mar 27 15:19:57 2023 -0400
  4. ef5c0b1 clk: renesas: Pack reset identifier before look up by Marek Vasut · Sat Mar 18 12:30:53 2023 +0100
  5. ea8505e clk: renesas: rcar-gen3: Replace SSCG caching with MDSEL/PE caching by Marek Vasut · Tue Feb 28 07:25:11 2023 +0100
  6. 06d8f97 clk: renesas: rcar-gen3: Factor out CPG library by Hai Pham · Thu Jan 26 21:06:07 2023 +0100
  7. 6811b57 clk: renesas: Add R8A77970 SD0H/SD0 clocks for SDHI by Hai Pham · Thu Jan 26 21:06:06 2023 +0100
  8. 4dae076 clk: renesas: Switch to new SD clock handling by Hai Pham · Sun Jan 29 02:50:22 2023 +0100
  9. 85e691e clk: renesas: Handle E3/D3 RPCSRC clock by Hai Pham · Thu Jan 26 21:06:04 2023 +0100
  10. e83700a clk: renesas: Introduce and use rcar_clk_get_rate64_div_table function by Hai Pham · Thu Jan 26 21:06:03 2023 +0100
  11. b2970fd clk: renesas: Convert Gen2/Gen3 clock tables to clk-provider struct clk_div_table by Marek Vasut · Thu Jan 26 21:06:02 2023 +0100
  12. 1bd2521 clk: renesas: Drop core param from gen3_clk_get_rate64_pll_mul_reg by Marek Vasut · Thu Jan 26 21:02:05 2023 +0100
  13. a80b061 clk: renesas: Use pre-defined offset for RPC clocks by Hai Pham · Thu Jan 26 21:02:04 2023 +0100
  14. f6b3202 clk: renesas: Add and enable CPG reset driver by Marek Vasut · Thu Jan 26 21:02:03 2023 +0100
  15. 569acef clk: renesas: Synchronize R8A779A0 V3U clock tables with Linux 6.1.7 by Marek Vasut · Thu Jan 26 21:01:56 2023 +0100
  16. 0985e0e clk: renesas: Add dummy SDnH clock by Hai Pham · Thu Jan 26 21:01:49 2023 +0100
  17. a1b654b treewide: invaild -> invalid by Sean Anderson · Wed Dec 01 14:26:53 2021 -0500
  18. 86d59f3 clk: renesas: Add R8A779A0 clock tables by Hai Pham · Tue Aug 11 10:46:34 2020 +0700
  19. 0fbb8a7 clk: renesas: Handle R8A779A0 V3U clock types in Gen3 clock code by Marek Vasut · Tue Apr 27 19:52:53 2021 +0200
  20. 8f56786 clk: renesas: Deduplicate gen3_clk_get_rate64() PLL handling by Marek Vasut · Tue Apr 27 19:36:39 2021 +0200
  21. 9480346 clk: renesas: Add register pointers into struct cpg_mssr_info by Hai Pham · Thu Nov 05 22:30:37 2020 +0700
  22. 5460ee0 clk: renesas: Pass struct cpg_mssr_info to renesas_clk_endisable() by Hai Pham · Fri May 22 10:39:04 2020 +0700
  23. 814217e clk: renesas: Make reset controller modemr register offset configurable by Marek Vasut · Sun Apr 25 21:53:05 2021 +0200
  24. 215de2b clk: renesas: Add support for RPCD2 clock by Hai Pham · Tue Aug 11 10:25:28 2020 +0700
  25. f2279df clk: renesas: Fix incorrect return RPC clk_get_rate by Hai Pham · Sat Dec 05 09:35:40 2020 +0700
  26. 3ba929a common: Drop asm/global_data.h from common header by Simon Glass · Fri Oct 30 21:38:53 2020 -0600
  27. 1096ae1 treewide: convert (void *)devfdt_get_addr() to dev_read_addr_ptr() by Masahiro Yamada · Fri Jul 17 14:36:46 2020 +0900
  28. 5a9ecb2 Revert "Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dm" by Tom Rini · Fri Jul 24 08:42:06 2020 -0400
  29. a3332a1 treewide: convert (void *)devfdt_get_addr() to dev_read_addr_ptr() by Masahiro Yamada · Fri Jul 17 14:36:46 2020 +0900
  30. 4dcacfc common: Drop linux/bitops.h from common header by Simon Glass · Sun May 10 11:40:13 2020 -0600
  31. 0f2af88 common: Drop log.h from common header by Simon Glass · Sun May 10 11:40:05 2020 -0600
  32. 7841483 clk: renesas: Synchronize Gen3 tables with Linux 5.0 by Marek Vasut · Mon Mar 04 21:38:10 2019 +0100
  33. c26bf89 clk: renesas: Allow reconfiguring SDHI clock on Gen3 by Marek Vasut · Tue Oct 30 17:54:20 2018 +0100
  34. 69459b2 clk: renesas: Add PE clock handling by Marek Vasut · Thu May 31 19:47:42 2018 +0200
  35. 52389f0 clk: renesas: Add PLL1 and PLL3 dividers by Marek Vasut · Thu May 31 19:25:41 2018 +0200
  36. 7571ac4 clk: renesas: Pass clock rate around as 64bit number internally by Marek Vasut · Thu May 31 19:06:02 2018 +0200
  37. 31de3d8 clk: renesas: Fix swapped arguments in debug message by Marek Vasut · Thu May 31 18:56:35 2018 +0200
  38. 10e4779 SPDX: Convert all of our single license tags to Linux Kernel style by Tom Rini · Sun May 06 17:58:06 2018 -0400
  39. 414dbbe clk: rmobile: Assure SD-IF clock are configured correctly by Marek Vasut · Thu Jan 11 16:28:31 2018 +0100
  40. e11008b clk: renesas: Split out code shared between Gen2 and Gen3 by Marek Vasut · Mon Jan 15 16:44:39 2018 +0100
  41. 2eb56a1 clk: renesas: Split SMSTPCR and RMSTPCR tables by Marek Vasut · Mon Jan 15 00:58:35 2018 +0100
  42. 28f9004 clk: renesas: Make PLL configurations per-SoC by Marek Vasut · Tue Jan 16 19:23:17 2018 +0100
  43. b923419 clk: renesas: Make clk_ids per-driver by Marek Vasut · Mon Jan 08 16:05:28 2018 +0100
  44. 4eb4e6e clk: renesas: Split RCar Gen3 driver by Marek Vasut · Mon Jan 08 14:01:40 2018 +0100
  45. fb0aa29 clk: rmobile: Add R8A77995 D3 clock tables by Marek Vasut · Sun Oct 08 21:09:15 2017 +0200
  46. 3f1a3a1 clk: rmobile: Add R8A77970 V3M clock tables by Marek Vasut · Mon Oct 09 20:52:33 2017 +0200
  47. 314ecf6 clk: rmobile: Fix typo in R8A7796 RPC clock table entry by Marek Vasut · Thu Nov 30 03:01:52 2017 +0100
  48. f0c152f clk: rmobile: Add R8A7796 xHCI clock by Marek Vasut · Fri Nov 10 23:17:51 2017 +0100
  49. df6a114 clk: rmobile: Move preboot clock shutdown to the driver by Marek Vasut · Sat Nov 25 22:08:55 2017 +0100
  50. c1aee32 clk: rmobile: Add RPC hyperflash clock by Marek Vasut · Fri Sep 15 21:10:29 2017 +0200
  51. 5a51be5 clk: rmobile: Add support for setting SDxCKCR by Marek Vasut · Fri Sep 15 21:10:08 2017 +0200
  52. 9390109 clk: rmobile: Split R8A7795 and R8A7796 core clock tables by Marek Vasut · Sun Aug 20 17:13:39 2017 +0200
  53. f3b8bf7 clk: rmobile: Add RCar Gen3 clock driver by Marek Vasut · Fri Jul 21 23:18:03 2017 +0200