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git01.mediatek.com / filogic / uboot / 591a9634501eb27f32087018e815e11160a81133 / drivers / clk / mediatek / clk-mtk.h
  1. c05ebe6 clk: mediatek: implement MUX_FLAGS and MUX_MIXED_FLAGS macro by Christian Marangi · Fri Jun 28 19:40:55 2024 +0200
  2. 29771ad clk: mediatek: add support for remapping clock ID by Christian Marangi · Fri Jun 28 19:40:54 2024 +0200
  3. e03d080 clk: mediatek: provide common clk init function for infrasys by Christian Marangi · Fri Jun 28 19:40:53 2024 +0200
  4. a4143eb clk: mediatek: add support for parent mux from different source by Christian Marangi · Fri Jun 28 19:40:50 2024 +0200
  5. baa244c clk: mediatek: add support for gates in clk_tree for infrasys by Christian Marangi · Fri Jun 28 19:40:48 2024 +0200
  6. f724f11 clk: mediatek: add CLK_XTAL support for clock driver by developer · Fri Sep 09 20:00:07 2022 +0800
  7. ad5b075 clk: mediatek: add infrasys clock mux support by developer · Fri Sep 09 20:00:04 2022 +0800
  8. fd47f76 clk: mediatek: add support to configure clock driver parent by developer · Fri Sep 09 20:00:01 2022 +0800
  9. 2dc4caa clk: mediatek: add CLK_BYPASS_XTAL flag to allow bypassing searching clock parent of xtal clock by developer · Fri Sep 09 19:59:59 2022 +0800
  10. 4dcacfc common: Drop linux/bitops.h from common header by Simon Glass · Sun May 10 11:40:13 2020 -0600
  11. 0b5e5f1 clk: mediatek: add configurable pcw_chg_reg/ibits/fmin to mtk_pll by developer · Tue Dec 31 11:29:22 2019 +0800
  12. ba560c7 clk: mediatek: add set_clr_upd mux type flow by developer · Tue Dec 31 11:29:21 2019 +0800
  13. a588d15 clk: MediaTek: add hifsys entry for MT7623 SoC. by developer · Mon Jul 29 22:17:48 2019 +0800
  14. 0225945 clk: MediaTek: bind ethsys reset controller by developer · Thu Dec 20 16:12:52 2018 +0800
  15. 2186c98 clk: MediaTek: add clock driver for MT7629 SoC. by developer · Thu Nov 15 10:07:54 2018 +0800