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git01.mediatek.com / filogic / uboot / 57281c3cfbbe332ba05bc5e89209e501d01e0268 / board / freescale / mpc8560ads / ddr.c
  1. a06d74c fsl-ddr: use the 1T timing as default configuration by Dave Liu · Fri Nov 21 16:31:43 2008 +0800
  2. fa44036 Pass dimm parameters to populate populate controller options by Haiying Wang · Fri Oct 03 12:36:55 2008 -0400
  3. 99d5071 FSL DDR: Convert MPC8560ADS to new DDR code. by Jon Loeliger · Tue Mar 18 11:12:44 2008 -0500