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git01.mediatek.com / filogic / uboot / 5709649ef949f9c84fc66cd34ed9e067b6dfb784 / arch / arm / mach-tegra / tegra114 / clock.c
  1. 0fca329 ARM: tegra114: Clear IDDQ when enabling PLLC by Thierry Reding · Tue Sep 08 11:38:04 2015 +0200
  2. 4c3aaa7 ARM: tegra: clk_m is the architected timer source clock by Thierry Reding · Thu Aug 20 11:42:20 2015 +0200
  3. 366b24f of: clean up OF_CONTROL ifdef conditionals by Masahiro Yamada · Wed Aug 12 07:31:55 2015 +0900
  4. a8480ef Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc. by Tom Warren · Thu Jun 25 09:50:44 2015 -0700
  5. ed1632a ARM: tegra: collect SoC sources into mach-tegra by Masahiro Yamada · Fri Feb 20 17:04:04 2015 +0900[Renamed from arch/arm/cpu/tegra114-common/clock.c]
  6. 2a544db ARM: tegra: don't exceed AVP limits when configuring PLLP by Jimmy Zhang · Fri Jan 24 10:37:36 2014 -0700
  7. 510c0ae ARM: tegra: rename MASK_BITS_29_28 to MASK_BITS_31_28 by Stephen Warren · Fri Jan 24 10:16:18 2014 -0700
  8. ea21e76 ARM: tegra: deduplicate MASK_BITS_xxx clock mux enum by Tom Warren · Fri Jan 24 10:16:17 2014 -0700
  9. fbef355 Tegra114: Initialize System Counter (TSC) with osc frequency by Tom Warren · Mon Apr 01 15:48:54 2013 -0700
  10. e3d95bc Tegra114: Add common CPU (shared) files by Tom Warren · Mon Jan 28 13:32:10 2013 +0000