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git01.mediatek.com / filogic / uboot / 56d1290ae4ab6aa71da103e0c2f8dc5b8c83d72e / arch / arm / mach-socfpga / board.c
  1. 8fdb419 ARM: socfpga: Reorder Arria10 SPL by Marek Vasut · 6 years ago
  2. 911a665 ARM: socfpga: Assure correct CPACR configuration by Marek Vasut · 6 years ago
  3. 27f05ac arm: socfpga: Fix: Compile MCR instruction on ARM 32-bit only by Ley Foon Tan · 6 years ago
  4. 72cc958 ARM: socfpga: Assure correct ACTLR configuration by Marek Vasut · 7 years ago
  5. f3f525c ARM: socfpga: Adding SoCFPGA info for both SPL and U-Boot by Tien Fong Chee · 7 years ago
  6. a5bfce3 ARM: socfpga: Adding clock frequency info for U-Boot by Tien Fong Chee · 7 years ago
  7. 3710de7 ARM: socfpga: Add DRAM bank size initialization function by Tien Fong Chee · 7 years ago
  8. 10e4779 SPDX: Convert all of our single license tags to Linux Kernel style by Tom Rini · 7 years ago
  9. 05204f6 arm: socfpga: Introduce common board code by Marek Vasut · 9 years ago