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git01.mediatek.com / filogic / uboot / 55a99219b496bfe32d867db76645b841def9ee8f / board / altera / arria5-socdk / qts / pll_config.h
  1. af42e2a arm: socfpga: Fix ArriaV SoCDK PLL config by Marek Vasut · Wed Aug 19 07:46:49 2015 +0200
  2. 372f70d arm: socfpga: Switch to filtered QTS files by Marek Vasut · Mon Aug 10 21:21:07 2015 +0200
  3. 3f4c561 arm: socfpga: Split Altera socfpga into AV and CV SoCDK by Marek Vasut · Mon Aug 10 21:24:53 2015 +0200[Renamed from board/altera/socfpga/qts/pll_config.h]
  4. 20a0739 arm: socfpga: Move generated files into qts subdir by Marek Vasut · Sat Jul 25 08:22:21 2015 +0200[Renamed from board/altera/socfpga/pll_config.h]
  5. b1194c2 arm: socfpga: spl: update peripheral pll for dev kit by Dinh Nguyen · Wed Apr 15 16:44:33 2015 -0500
  6. 3debe33 arm: socfpga: Sync Cyclone V DK PLL configuration by Marek Vasut · Tue Dec 30 19:41:17 2014 +0100
  7. 43dca1e arm: socfpga: clock: Add missing stubs into board file by Marek Vasut · Sat Sep 13 08:16:49 2014 +0200
  8. cb35060 socfpga: Adding Clock Manager driver by Chin Liang See · Tue Mar 04 22:13:53 2014 -0600