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git01.mediatek.com / filogic / uboot / 54fb0a47d11fe92095d6b4bb143ced8ff456fe4f / drivers / ddr / marvell
  1. 31fdba2 arm: mvebu: a38x: Weed out floating point use by Marek Vasut · Sat Apr 30 14:45:42 2016 +0200
  2. edfdb99 Fix spelling of "occurred". by Vagrant Cascadian · Sat Apr 30 19:18:00 2016 -0700
  3. 5b2c16a arm: mvebu: Fix ddr3_init() cpu config by Dirk Eibach · Wed Oct 28 16:44:15 2015 +0100
  4. 7557405 Use correct spelling of "U-Boot" by Bin Meng · Fri Feb 05 19:30:11 2016 -0800
  5. d911168 mvebu: axp: Rename MV_DDR_32BIT to CONFIG_DDR_32BIT by Phil Sutter · Fri Dec 25 14:41:23 2015 +0100
  6. 33aa8de axp: Fix debugging support in DDR3 write leveling by Phil Sutter · Fri Dec 25 14:41:19 2015 +0100
  7. ff7ad17 arm: mvebu: Make ECC support configurable on Armada XP by Stefan Roese · Thu Dec 10 15:02:38 2015 +0100
  8. 3c6b6fc arm: mvebu: ddr: Fix compilation warning by Stefan Roese · Thu Nov 19 13:50:10 2015 +0100
  9. dea4e33 arm: mvebu: Fix SAR1_CPU_CORE_MASK by Dirk Eibach · Wed Oct 28 16:44:14 2015 +0100
  10. 0277a6b arm: mvebu: a38x: Remove unsupported topologies by Kevin Smith · Fri Oct 23 17:53:19 2015 +0000
  11. 69bab55 bitops: introduce BIT() definition by Heiko Schocher · Mon Sep 07 13:43:52 2015 +0200
  12. f3345e6 arm: mvebu: Add complete SDRAM ECC scrubbing by Stefan Roese · Thu Aug 06 14:43:13 2015 +0200
  13. e4a0f27 arm: mvebu: sdram: Enable ECC support on Armada XP by Stefan Roese · Tue Aug 11 17:08:01 2015 +0200
  14. 61cee0a arm: mvebu: a38x: Use correct PEX register access macros by Stefan Roese · Mon Jun 08 17:01:26 2015 +0200
  15. 5ffceb8 arm: mvebu: Add Armada 38x DDR3 training code from Marvell bin_hdr by Stefan Roese · Thu Mar 26 15:36:56 2015 +0100
  16. eb753e9 arm: mvebu: drivers/ddr: Move Armada XP DDR init code into new directory by Stefan Roese · Wed Mar 25 12:51:18 2015 +0100