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git01.mediatek.com / filogic / uboot / 541f62c2f923a1ae4b182ce19d45830154f7e264 / arch / riscv / lib / andes_plic.c
  1. 28bfc32 riscv: Clean up initialization in Andes PLIC by Sean Anderson · Mon Sep 28 10:52:25 2020 -0400
  2. d2014d1 riscv: remove redundant logical constraint. by Heinrich Schuchardt · Mon Aug 03 23:33:42 2020 +0200
  3. b1d0cb3 riscv: Clean up IPI initialization code by Sean Anderson · Wed Jun 24 06:41:18 2020 -0400
  4. d66c5f7 dm: core: Require users of devres to include the header by Simon Glass · Mon Feb 03 07:36:15 2020 -0700
  5. c7460b8 riscv: add functions for reading the IPI status by Lukas Auer · Sun Dec 08 23:28:50 2019 +0100
  6. eb61303 riscv: andes_plic: Fix some wrong configurations by Rick Chen · Thu Nov 14 13:52:24 2019 +0800
  7. eaae83b riscv: andes_plic: init plic by scanning each cpu node by Rick Chen · Wed Aug 21 11:26:50 2019 +0800
  8. 6df4ed0 riscv: Add a SYSCON driver for Andestech's PLIC by Rick Chen · Tue Apr 02 15:56:39 2019 +0800