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git01.mediatek.com / filogic / uboot / 4dc1de3d68cb08c7294c0a490bab2fdd402200e7 / drivers / clk / clk_stm32mp1.c
  1. 4cb3b53 clk: stm32mp1: Add VREF clock gating by Fabrice Gasnier · Thu Apr 26 17:00:47 2018 +0200
  2. 8b0c8a1 SPDX: Convert all of our multiple license tags to Linux Kernel style by Tom Rini · Sun May 06 18:27:01 2018 -0400
  3. bf7d944 clock: stm32mp1: add stgen clock source change support by Patrick Delaunay · Tue Mar 20 11:41:25 2018 +0100
  4. f11398e clk: stm32mp1: add clock tree initialization by Patrick Delaunay · Mon Mar 12 10:46:16 2018 +0100
  5. e6ab627 clk: add driver for stm32mp1 by Patrick Delaunay · Mon Mar 12 10:46:15 2018 +0100