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git01.mediatek.com / filogic / uboot / 49568feff1e123d4b24079b0b8e92704658912b6 / arch / arm / dts / zynqmp-clk.dtsi
  1. 088fb5d arm64: zynqmp: Enable cadence WDT for zcu100 by Michal Simek · Thu Apr 19 15:43:50 2018 +0200
  2. 10aac09 arm64: zynqmp: Get 200MHz clock early for MMC by Michal Simek · Wed Apr 04 10:41:35 2018 +0200
  3. 090a2d7 arm64: zynqmp: Sync up license with mainline kernel by Michal Simek · Tue Mar 27 10:36:39 2018 +0200
  4. 63e5dd5 arm64: zynqmp: Move nodes which have no reg property out of bus by Michal Simek · Wed Jul 05 14:51:42 2017 +0200
  5. 6e94aad ARM64: zynqmp: clk: Add the clock for watchdog by Shubhrajyoti Datta · Fri Oct 21 16:12:19 2016 +0530
  6. 8483b94 ARM64: zynqmp: Add clocks for LPDDMA by Kedareswara rao Appana · Fri Sep 09 12:36:00 2016 +0530
  7. 0f20ffb ARM64: zynqmp: Add u-boot,dm-pre-reloc to clk nodes by Michal Simek · Fri Jul 29 13:03:29 2016 +0200
  8. 5fc61c8 ARM64: zynqmp: Add support for ZCU102 platform by Michal Simek · Thu Apr 07 15:58:23 2016 +0200