Gitiles
Code Review
Sign In
git01.mediatek.com
/
filogic
/
uboot
/
4812a38a30001136dcc5bf41f424bff338ee7fc5
/
arch
/
arm
/
dts
/
mt7986.dtsi
07603e4
clk: mediatek: mt7986: rename CK to CLK
by Christian Marangi
· Sat Aug 03 10:40:48 2024 +0200
bf79ce0
clk: mediatek: mt7986: convert to unified infracfg gates + muxes
by Christian Marangi
· Sat Aug 03 10:40:47 2024 +0200
0fc50e7
clk: mediatek: mt7986: drop 1/1 spurious factor for topckgen
by Christian Marangi
· Sat Aug 03 10:40:43 2024 +0200
9276f07
clk: mediatek: mt7986: rename TOPCKGEN factor clock to upstream naming
by Christian Marangi
· Sat Aug 03 10:40:41 2024 +0200
ab4de13
clk: mediatek: mt7986: drop 1/1 infracfg spurious factor
by Christian Marangi
· Sat Aug 03 10:40:38 2024 +0200
0178c61
clk: mediatek: mt7986: rename CB_CKSQ_40M to TOP_XTAL
by Christian Marangi
· Sat Aug 03 10:40:35 2024 +0200
d3a98cb
dm: dts: Convert driver model tags to use new schema
by Simon Glass
· Mon Feb 13 08:56:33 2023 -0700
e021c15
arm: mediatek: add support for MediaTek MT7986 SoC
by developer
· Fri Sep 09 19:59:09 2022 +0800