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git01.mediatek.com / filogic / uboot / 47e90456ed7a210ca4b23f96621722ca6d8c8c83 / arch / arm / dts / zynq-cse-nor.dts
  1. c1bb21b arm: zynq: Fix indentation for zynq-cse targets by Michal Simek · Fri Jul 20 10:17:17 2018 +0200
  2. bd35b56 arm: zynq: Remove fclk-enable property for cse-nor target by Michal Simek · Fri Jul 20 10:16:21 2018 +0200
  3. f3e0ed4 arm: zynq: Add parallel NOR flash mini u-boot configuration for zynq by Siva Durga Prasad Paladugu · Mon Jul 16 15:57:02 2018 +0530