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git01.mediatek.com / filogic / uboot / 47c05806d8abdfea3c74b8c29c22681de4e39606 / arch / arm / mach-sunxi / dram_sun50i_h6.c
  1. 16f6f79 sunxi: dram: make MBUS configuration functions static by Andre Przywara · Wed Jun 07 01:07:41 2023 +0100
  2. e04cd49 sunxi: prcm: Add a few registers by Jernej Skrabec · Sun Jan 30 15:27:13 2022 +0100
  3. 0f7c8bc sunxi: clock: H6/H616: Fix PLL clock factor encodings by Andre Przywara · Wed May 05 13:53:05 2021 +0100
  4. 738334f sunxi: dram: h6: Improve DDR3 config detection by Jernej Skrabec · Thu Mar 12 17:46:00 2020 +0000
  5. dbd7954 common: Drop linux/delay.h from common header by Simon Glass · Sun May 10 11:40:11 2020 -0600
  6. 0f2af88 common: Drop log.h from common header by Simon Glass · Sun May 10 11:40:05 2020 -0600
  7. 9758973 common: Drop init.h from common header by Simon Glass · Sun May 10 11:40:02 2020 -0600
  8. 370245e sunxi: H6: DRAM: Add support for half DQ by Jernej Skrabec · Fri Aug 23 19:24:04 2019 +0200
  9. fed1d2f sunxi: H6: Add DDR3 DRAM delay values by Jernej Skrabec · Mon Jul 15 02:27:09 2019 +0100
  10. c78a47a sunxi: H6: Add DDR3 support to DRAM controller driver by Andre Przywara · Mon Jul 15 02:27:07 2019 +0100
  11. 1c7a751 sunxi: H6: move LPDDR3 timing definition into separate file by Andre Przywara · Mon Jul 15 02:27:06 2019 +0100
  12. 595475e sunxi: H6: DRAM: follow recommended PHY init algorithm by Andre Przywara · Mon Jul 15 02:27:05 2019 +0100
  13. de5d61f sunxi: H6: DRAM: avoid memcpy() on MMIO registers by Andre Przywara · Mon Jul 15 02:27:04 2019 +0100
  14. ac2ed96 sunxi: fix DRAM gate/reset sequence of H6 by Icenowy Zheng · Sat Oct 06 23:23:32 2018 +0800
  15. 4e287f6 sunxi: add DRAM support to H6 by Icenowy Zheng · Mon Jul 23 06:13:34 2018 +0800