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git01.mediatek.com / filogic / uboot / 47af53c6bd0134a21e37a942134a0f940ddf2fec / drivers / ram / stm32mp1 / stm32mp1_ddr_regs.h
  1. 5225bb8 ram: stm32mp1: Unconditionally enable ASR by Marek Vasut · Fri Feb 25 02:15:58 2022 +0100
  2. df7fe21 ram: stm32mp1: compute DDR size from DDRCTL registers by Patrick Delaunay · Wed Nov 24 10:52:18 2021 +0100
  3. 0c4354e stm32mp1: ram: remove tuning support by Patrick Delaunay · Mon Nov 15 15:32:30 2021 +0100
  4. a709d63 stm32mp1: ram: add read valid training support by Patrick Delaunay · Mon Nov 15 15:32:28 2021 +0100
  5. 4dcacfc common: Drop linux/bitops.h from common header by Simon Glass · Sun May 10 11:40:13 2020 -0600
  6. eca9bc0 ram: stm32mp1_ddr: fix self refresh disable during DQS training by Patrick Delaunay · Fri Mar 06 11:14:09 2020 +0100
  7. 2f91e61 stm32mp1: ram: add tuning in DDR interactive mode by Patrick Delaunay · Wed Apr 10 14:09:29 2019 +0200
  8. 4175f45 stm32mp1: ram: add support for LPDDR2/LPDDR3 by Patrick Delaunay · Wed Apr 10 14:09:26 2019 +0200
  9. 8b0c8a1 SPDX: Convert all of our multiple license tags to Linux Kernel style by Tom Rini · Sun May 06 18:27:01 2018 -0400
  10. 939d536 ram: stm32mp1: add driver by Patrick Delaunay · Mon Mar 12 10:46:11 2018 +0100