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git01.mediatek.com / filogic / uboot / 43358c80c49d0e0432005ee4d8fa7e4ba49590f8 / drivers / clk / microchip / mpfs_clk.c
  1. 73a1d60 clk: microchip: mpfs: fix periph clk parentage by Conor Dooley · Tue Oct 25 08:58:47 2022 +0100
  2. d4bbef0 clk: microchip: mpfs: fix reference clock handling by Conor Dooley · Tue Oct 25 08:58:46 2022 +0100
  3. 4a182e0 clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() by Conor Dooley · Tue Oct 25 08:58:45 2022 +0100
  4. 35c8464 clk: Use generic CCF ops where possible by Sean Anderson · Sun Mar 20 16:34:46 2022 -0400
  5. 3ff5d69 clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag by Bin Meng · Wed Mar 31 15:24:49 2021 +0800
  6. 0c4ae80 clk: Add Microchip PolarFire SoC clock driver by Padmarao Begari · Fri Jan 15 08:20:38 2021 +0530