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git01.mediatek.com / filogic / uboot / 42c213ae4f609e0742a1660948bd1d55110b8ce4 / arch / powerpc / cpu / ppc4xx / sdram.c
  1. bd8ec7e Coding Style cleanup: remove trailing white space by Wolfgang Denk · Mon Oct 07 13:07:26 2013 +0200
  2. d79de1d Add GPL-2.0+ SPDX-License-Identifier to source files by Wolfgang Denk · Mon Jul 08 09:37:19 2013 +0200
  3. 247e9d7 ppc4xx: Move ppc4xx headers to powerpc include directory by Stefan Roese · Thu Sep 09 19:18:00 2010 +0200
  4. 88fbf93 Move arch/ppc to arch/powerpc by Stefan Roese · Thu Apr 15 16:07:28 2010 +0200[Renamed from arch/ppc/cpu/ppc4xx/sdram.c]
  5. 29514c7 ppc: Move cpu/$CPU to arch/ppc/cpu/$CPU by Peter Tyser · Mon Apr 12 22:28:09 2010 -0500[Renamed from cpu/ppc4xx/sdram.c]
  6. 6987e65 ppc4xx: Convert PPC4xx SDRAM defines from lower case to upper case by Stefan Roese · Thu Sep 24 13:59:57 2009 +0200
  7. 918010a ppc4xx: Big cleanup of PPC4xx defines by Stefan Roese · Wed Sep 09 16:25:29 2009 +0200
  8. 09fe652 ppc4xx: Improve DDR autodetect by Dirk Eibach · Tue Dec 09 11:00:07 2008 +0100
  9. 0383694 rename CFG_ macros to CONFIG_SYS by Jean-Christophe PLAGNIOL-VILLARD · Thu Oct 16 15:01:15 2008 +0200
  10. 58296a1 ppc4xx: Fix SDRAM inititialization of multiple 405 based board ports by Stefan Roese · Wed Sep 10 16:53:47 2008 +0200
  11. bd99ae7 Change initdram() return type to phys_size_t by Becky Bruce · Mon Jun 09 16:03:40 2008 -0500
  12. cdb0470 ppc4xx: Remove superfluous dram_init() call or replace it by initdram() by Stefan Roese · Mon Jun 02 17:37:28 2008 +0200
  13. b693341 ppc4xx: Enable Primordial Stack for 40x and Unify ECC Handling by Grant Erickson · Thu May 22 14:44:14 2008 -0700
  14. a5d182e ppc4xx: Add initial Zeus (PPC405EP) board support by Stefan Roese · Tue Aug 14 14:44:41 2007 +0200
  15. 9aa3677 ppc4xx: Add support for AMCC 405EP Taihu board by John Otken · Thu Jul 26 17:49:11 2007 +0200
  16. 8d98230 [PATCH] Add support for AMCC Taishan PPC440GX eval board by Stefan Roese · Thu Jan 18 10:25:34 2007 +0100
  17. 76e3d2a [PATCH] 44x: Fix problem with DDR controller setup (refresh rate) by Stefan Roese · Sat Jan 06 15:58:09 2007 +0100
  18. 4963968 Add initial support for the ALPR board from Prodrive by Stefan Roese · Tue Aug 15 14:22:35 2006 +0200
  19. e335ee0 PPC440 DDR setup: Set SDRAM0_CFG0[PMU]=0 for best performance by Stefan Roese · Fri Jul 28 18:34:58 2006 +0200
  20. ebd3deb Some code cleanup by Wolfgang Denk · Sun Apr 16 10:51:58 2006 +0200
  21. fd63793 Updates to common PPC4xx onboard (DDR)SDRAM init code (405 and 440) by Stefan Roese · Fri Mar 17 10:28:24 2006 +0100
  22. c443fe9 Add support for Prodrive P3P440 board: by Stefan Roese · Tue Nov 22 13:20:42 2005 +0100
  23. 55ca749 cpu/ppc4xx/sdram.c rewritten now using get_ram_size() by stroese · Thu Jul 15 14:41:13 2004 +0000
  24. c45cfd0 Disable memory controller before setting first values. by stroese · Fri Sep 12 08:49:58 2003 +0000
  25. 57b2d80 * Code cleanup: by wdenk · Fri Jun 27 21:31:46 2003 +0000
  26. 41e2e05 Cleanup: remove trailing white space by wdenk · Tue Feb 11 01:49:43 2003 +0000
  27. 51c57b9 Added 4MByte and 128MByte onboard SDRAM by stroese · Mon Feb 10 16:26:37 2003 +0000
  28. c609719 Initial revision by wdenk · Sun Nov 03 00:24:07 2002 +0000