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git01.mediatek.com / filogic / uboot / 3d8b95051ac4e68fd1cdcd9895f505c0625ac3c9 / drivers / clk / clk_versal.c
  1. e3184f8 clk: versal: Mark versal_clock_setup() as static by Venkatesh Yadav Abbarapu · Fri Oct 07 16:25:35 2022 +0530
  2. d52796d clk: versal: Enable clock driver for Versal NET by Jay Buddhabhatti · Mon Sep 19 14:21:05 2022 +0200
  3. b5ef0ba clk: versal: Enable only GATE type clocks by T Karthik Reddy · Tue Sep 28 11:30:27 2021 +0530
  4. 277300f clk: versal: Add support to enable clocks by T Karthik Reddy · Wed Feb 03 03:10:47 2021 -0700
  5. 8a2b47f dm: treewide: Rename auto_alloc_size members to be shorter by Simon Glass · Thu Dec 03 16:55:17 2020 -0700
  6. 1a7c058 clk: versal: Move pm_query_id out of clock driver by Michal Simek · Thu Jul 23 09:24:06 2020 +0200
  7. 98697a1 clk: versal: Remove alt_ref_clk from clock sources by Rajan Vaja · Mon May 04 22:53:56 2020 -0700
  8. 6b9f010 common: Drop asm/ptrace.h from common header by Simon Glass · Sun May 10 11:40:06 2020 -0600
  9. 0f2af88 common: Drop log.h from common header by Simon Glass · Sun May 10 11:40:05 2020 -0600
  10. 274e0b0 common: Drop net.h from common header by Simon Glass · Sun May 10 11:39:56 2020 -0600
  11. aa12d51 clk: versal: Fix watchdog clock issue by T Karthik Reddy · Wed Apr 08 21:34:54 2020 -0600
  12. 5986efc versal: drivers: clk: Fix invalid clock name queries by Rajan Vaja · Thu Jan 16 03:55:05 2020 -0800
  13. 9bc1564 dm: core: Create a new header file for 'compat' features by Simon Glass · Mon Feb 03 07:36:16 2020 -0700
  14. d66c5f7 dm: core: Require users of devres to include the header by Simon Glass · Mon Feb 03 07:36:15 2020 -0700
  15. 142fb5b arm64: versal: Rename versal_pm_request to xilinx_pm_request by Michal Simek · Fri Oct 04 15:52:43 2019 +0200
  16. e50c104 arm64: versal: Clean pm_api_id usage by Michal Simek · Fri Oct 04 15:25:18 2019 +0200
  17. f7a7120 clk: versal: Add clock driver support by Siva Durga Prasad Paladugu · Sun Jun 23 12:24:57 2019 +0530