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git01.mediatek.com / filogic / uboot / 3d6864a0884df833058c5cec50a452d8309b5b0a / arch / mips / lib / cache.c
  1. 3d6864a MIPS: Make CM GCR base configurable by Paul Burton · Fri May 12 13:26:11 2017 +0200
  2. 8156078 MIPS: L2 cache support by Paul Burton · Wed Sep 21 11:18:54 2016 +0100
  3. dc2037e MIPS: Probe cache line sizes once during boot by Paul Burton · Wed Sep 21 11:18:48 2016 +0100
  4. 1194f94 MIPS: Fix invalidate_dcache_range to operate on L1 Dcache by Paul Burton · Thu Jun 09 13:09:51 2016 +0100
  5. a97d593 MIPS: Abstract cache op loops with a macro by Paul Burton · Fri May 27 14:28:06 2016 +0100
  6. 62f1352 MIPS: Split I & D cache line size config by Paul Burton · Fri May 27 14:28:05 2016 +0100
  7. 5e51142 MIPS: Move cache sizes to Kconfig by Paul Burton · Fri May 27 14:28:04 2016 +0100
  8. 0e50ffc mips: cache: Bulletproof the code against cornercases by Marek Vasut · Wed Jan 27 03:13:59 2016 +0100
  9. a6dae71 MIPS: sync processor and register definitions with linux-4.4 by Daniel Schwierzeck · Tue Jan 12 21:48:26 2016 +0100
  10. 4ff6b10 MIPS: unify cache maintenance functions by Paul Burton · Thu Jan 29 01:27:57 2015 +0000