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git01.mediatek.com / filogic / uboot / 3ca8c4f956d9bc5f4eb9a7986435c688a4ef4cb5 / board / freescale / imx8ulp_evk / lpddr4_timing.c
  1. 4d23115 imx8ulp_evk: disable overflow of port0 for LPAV by Peng Fan · Tue Jan 31 16:42:33 2023 +0800
  2. 144e2b3 imx8ulp_evk: Update DDR ports arbitration for DCNANO underrun by Ye Li · Tue Jan 31 16:42:32 2023 +0800
  3. 6a2c906 imx8ulp_evk: Update the DDR timing by Jacky Bai · Tue Jan 31 16:42:30 2023 +0800
  4. 5e80148 imx: imx8ulp_evk: Update LPDDR4 PHY settings by Ye Li · Wed Apr 06 14:30:22 2022 +0800
  5. cbe5d38 arm: imx: add i.MX8ULP EVK support by Peng Fan · Sat Aug 07 16:01:13 2021 +0800