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git01.mediatek.com / filogic / uboot / 3a21671194ef8f7bd0c3d722ddcd5fc534d816a6 / drivers / clk / clk_kendryte.c
  1. e72139e clk: k210: Try harder to get the best config by Sean Anderson · Sat Sep 11 13:20:03 2021 -0400
  2. 89c3584 k210: clk: Refactor out_of_spec tests by Sean Anderson · Sat Sep 11 13:20:01 2021 -0400
  3. b0126e9 clk: k210: Fix checking if ulongs are less than 0 by Sean Anderson · Sat Sep 11 13:20:00 2021 -0400
  4. 152919d clk: k210: Move k210 clock out of its own subdirectory by Sean Anderson · Fri Jun 11 00:16:14 2021 -0400[Renamed from drivers/clk/kendryte/clk.c]
  5. 1a37182 clk: k210: Don't set PLL rates if we are already at the correct rate by Sean Anderson · Fri Jun 11 00:16:12 2021 -0400
  6. 3a29bc6 clk: k210: Re-add support for setting rate by Sean Anderson · Fri Jun 11 00:16:11 2021 -0400
  7. ecf9284 clk: k210: Implement soc_clk_dump by Sean Anderson · Fri Jun 11 00:16:10 2021 -0400
  8. edbe849 clk: k210: Move pll into the rest of the driver by Sean Anderson · Fri Jun 11 00:16:09 2021 -0400
  9. 2957313 clk: k210: Rewrite to remove CCF by Sean Anderson · Fri Jun 11 00:16:08 2021 -0400
  10. 95951fc Merge tag 'ti-v2021.10-next-v2' of https://source.denx.de/u-boot/custodians/u-boot-ti into next by Tom Rini · Sun Jun 13 07:48:22 2021 -0400