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git01.mediatek.com / filogic / uboot / 3281cb6ebb4c406a381538e2240166a87f3db0db / arch / riscv / lib / andes_plicsw.c
  1. 739cd6f riscv: Rename Andes PLIC to PLICSW by Yu Chien Peter Lin · Tue Oct 25 23:03:50 2022 +0800[Renamed (76%) from arch/riscv/lib/andes_plic.c]
  2. bcb208b riscv: andes_plic.c: use modified IPI scheme by Yu Chien Peter Lin · Fri Oct 14 15:00:18 2022 +0800
  3. 2e4938b dm: core: Drop ofnode_is_available() by Simon Glass · Tue Sep 06 20:27:17 2022 -0600
  4. b6ec26b riscv: andes_plic: Fix riscv_get_ipi() mask by Bin Meng · Tue Jun 15 13:45:57 2021 +0800
  5. 3ba929a common: Drop asm/global_data.h from common header by Simon Glass · Fri Oct 30 21:38:53 2020 -0600
  6. 28bfc32 riscv: Clean up initialization in Andes PLIC by Sean Anderson · Mon Sep 28 10:52:25 2020 -0400
  7. d2014d1 riscv: remove redundant logical constraint. by Heinrich Schuchardt · Mon Aug 03 23:33:42 2020 +0200
  8. b1d0cb3 riscv: Clean up IPI initialization code by Sean Anderson · Wed Jun 24 06:41:18 2020 -0400
  9. d66c5f7 dm: core: Require users of devres to include the header by Simon Glass · Mon Feb 03 07:36:15 2020 -0700
  10. c7460b8 riscv: add functions for reading the IPI status by Lukas Auer · Sun Dec 08 23:28:50 2019 +0100
  11. eb61303 riscv: andes_plic: Fix some wrong configurations by Rick Chen · Thu Nov 14 13:52:24 2019 +0800
  12. eaae83b riscv: andes_plic: init plic by scanning each cpu node by Rick Chen · Wed Aug 21 11:26:50 2019 +0800
  13. 6df4ed0 riscv: Add a SYSCON driver for Andestech's PLIC by Rick Chen · Tue Apr 02 15:56:39 2019 +0800