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git01.mediatek.com / filogic / uboot / 32645d75d6eb1ce322c60de8e8733bb4128e8ed1 / arch / riscv / cpu / fu540
  1. 4f4f583 board_f: Fix types for board_get_usable_ram_top() by Pali Rohár · Fri Sep 09 17:32:40 2022 +0200
  2. ec34849 board: sifive: use ccache driver instead of helper function by Zong Li · Wed Sep 01 15:01:42 2021 +0800
  3. ecefa5f drivers: clk: add fu740 support by Green Wan · Thu May 27 06:52:08 2021 -0700
  4. 614b1d8 riscv: Split SiFive CLINT support between SPL and U-Boot proper by Bin Meng · Tue May 11 20:04:12 2021 +0800
  5. b1b3bc0 Revert "riscv: cpu: fu740: clear feature disable CSR" by Bin Meng · Mon May 10 17:08:16 2021 +0800
  6. 968a13f riscv: cpu: fu740: clear feature disable CSR by Green Wan · Sun May 02 23:23:05 2021 -0700
  7. 2f00216 cpu: Rename SPL_CPU_SUPPORT to SPL_CPU by Simon Glass · Mon Mar 15 18:11:18 2021 +1300
  8. b1db71b Merge branch '2021-02-02-drop-asm_global_data-when-unused' by Tom Rini · Mon Feb 15 08:19:40 2021 -0500
  9. 489b25a riscv: Adjust board_get_usable_ram_top() for 32-bit by Bin Meng · Sun Jan 31 20:35:57 2021 +0800
  10. 3ba929a common: Drop asm/global_data.h from common header by Simon Glass · Fri Oct 30 21:38:53 2020 -0600
  11. 4f1b444 riscv: sifive/fu540: kconfig: Enable support for Opencores I2C controller by Pragnesh Patel · Sat Nov 14 14:42:35 2020 +0530
  12. 9baaaef riscv: Rework riscv timer driver to only support S-mode by Sean Anderson · Mon Sep 28 10:52:21 2020 -0400
  13. 54bcf26 riscv: fu540: Use correct API to get L2 cache controller base address by Bin Meng · Tue Aug 18 01:09:20 2020 -0700
  14. 03de50e riscv: sifive: fu540: redundant initialization by Heinrich Schuchardt · Mon Aug 03 23:09:49 2020 +0200
  15. 6b15551 riscv: sifive/fu540: kconfig: Move FU540 driver related options to the SoC level by Bin Meng · Sun Aug 02 23:09:04 2020 -0700
  16. 2b2d9c4 riscv: sifive/fu540: spl: Rename soc_spl_init() by Bin Meng · Sun Aug 02 23:09:03 2020 -0700
  17. e70ef90 env: Enable SPI flash env for SiFive FU540 by Jagan Teki · Wed Jul 15 15:39:00 2020 +0530
  18. 8a52128 riscv: sifive: fu540: enable all cache ways from U-Boot proper by Pragnesh Patel · Fri May 29 12:14:51 2020 +0530
  19. e00653c riscv: sifive: fu540: add SPL configuration by Pragnesh Patel · Fri May 29 11:33:35 2020 +0530
  20. 25269c0 riscv: cpu: fu540: Add support for cpu fu540 by Pragnesh Patel · Fri May 29 11:33:34 2020 +0530