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git01.mediatek.com / filogic / uboot / 313d80f17fc439533c5fbdbe3cb85e0ea625e6eb / drivers / clk / sunxi / clk_h6.c
  1. 751c6c6 clk: sunxi: Use a single driver for all variants by Samuel Holland · Mon May 09 00:29:34 2022 -0500
  2. 1567fdf reset: sunxi: Get the reset count from the CCU descriptor by Samuel Holland · Mon May 09 00:29:33 2022 -0500
  3. 8443650 clk: sunxi: Store the array sizes in the CCU descriptor by Samuel Holland · Mon May 09 00:29:31 2022 -0500
  4. 2d1864f clk: sunxi: add and use dummy gate clocks by Andre Przywara · Thu May 05 01:25:43 2022 +0100
  5. 3e9aa0b clk: sunxi: add PIO bus gate clocks by Andre Przywara · Wed May 04 22:10:28 2022 +0100
  6. fa7a7fa clk: sunxi: Add support for I2C gates/resets by Samuel Holland · Sun Sep 12 09:47:24 2021 -0500
  7. 12e3faa clk: sunxi: Move header out of arch directory by Samuel Holland · Sun Sep 12 11:48:43 2021 -0500
  8. d73b8a5 clk: sunxi: h6: Add XHCI clocks by Samuel Holland · Sun Feb 07 23:57:20 2021 -0600
  9. 8a2b47f dm: treewide: Rename auto_alloc_size members to be shorter by Simon Glass · Thu Dec 03 16:55:17 2020 -0700
  10. 4dcacfc common: Drop linux/bitops.h from common header by Simon Glass · Sun May 10 11:40:13 2020 -0600
  11. 60e6efd sunxi: clocks: Add H6 USB clock gates and resets by Andre Przywara · Sun Jun 23 15:09:48 2019 +0100
  12. 836631b clk: sunxi: Implement EMAC, GMAC clocks, resets by Jagan Teki · Thu Feb 28 00:26:57 2019 +0530
  13. bc12313 clk: sunxi: Implement SPI clocks, resets by Jagan Teki · Wed Feb 27 20:02:06 2019 +0530
  14. ddf33c1 sunxi: clk: add MMC gates/resets by Andre Przywara · Tue Jan 29 15:54:09 2019 +0000
  15. 5bc16d2 clk: sunxi: Add Allwinner H6 CLK driver by Jagan Teki · Mon Dec 31 15:35:01 2018 +0530