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git01.mediatek.com / filogic / uboot / 30c4b86449836f4a4ebbdda163e517a49b87dfa8 / drivers / clk / mediatek / clk-mt7986.c
  1. 30c4b86 clk: mediatek: mt7986: fix typo for infra_i2c0_ck by Christian Marangi · Sat Aug 03 10:40:40 2024 +0200
  2. 6a89a38 clk: mediatek: mt7986: add missing entry for IPCIE_PIPE_CK infra gate by Christian Marangi · Sat Aug 03 10:40:39 2024 +0200
  3. ab4de13 clk: mediatek: mt7986: drop 1/1 infracfg spurious factor by Christian Marangi · Sat Aug 03 10:40:38 2024 +0200
  4. 76052a2 clk: mediatek: mt7986: fix wrong parent for INFRA_ADC_26M_CK by Christian Marangi · Sat Aug 03 10:40:37 2024 +0200
  5. 7739a5f clk: mediatek: mt7986: rename 66M_MCK to SYSAXI_D2 by Christian Marangi · Sat Aug 03 10:40:36 2024 +0200
  6. 0178c61 clk: mediatek: mt7986: rename CB_CKSQ_40M to TOP_XTAL by Christian Marangi · Sat Aug 03 10:40:35 2024 +0200
  7. d349194 clk: mediatek: mt7986: fix wrong shift for PCIe clocks by Christian Marangi · Sat Aug 03 10:40:34 2024 +0200
  8. 4dd4a28 clk: mediatek: mt7986: support alternative compatible for fixed-plls by Christian Marangi · Mon Jun 24 23:03:40 2024 +0200
  9. 37161fe clk: mediatek: add clock driver support for MediaTek MT7986 SoC by developer · Fri Sep 09 20:00:09 2022 +0800