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git01.mediatek.com / filogic / uboot / 2ec41ef56ed21d53df02e48c82de219606b8738e / arch / riscv / cpu / ax25
  1. 49cb706 riscv: cache: use CCTL to flush d-cache by Rick Chen · 5 years ago
  2. 05a684e riscv: cache: Flush L2 cache before jump to linux by Rick Chen · 5 years ago
  3. 19117d2 riscv: ax25: add imply v5l2 cache controller by Rick Chen · 5 years ago
  4. 6134659 riscv: add run mode configuration for SPL by Lukas Auer · 5 years ago
  5. 43ec7e0 CONFIG_SPL_SYS_[DI]CACHE_OFF: add by Trevor Woerner · 6 years ago
  6. f71410a riscv: ax25: Andes specific cache shall only support in M-mode by Rick Chen · 6 years ago
  7. 14a1075 riscv: ax25: Add platform-specific Kconfig options by Rick Chen · 6 years ago
  8. 6280e32 riscv: move the AX25-specific implementation of flush_dcache_all by Lukas Auer · 6 years ago
  9. 4b284ad riscv: ax25: Hide the ax25-specific Kconfig option by Bin Meng · 6 years ago
  10. 842d580 riscv: cache: Implement i/dcache [status, enable, disable] by Rick Chen · 6 years ago
  11. de8d80e riscv: Move do_reset() to a common place by Bin Meng · 6 years ago
  12. bcb3843 riscv: Make start.S available for all targets by Bin Meng · 6 years ago
  13. a28e0f5 riscv: Move the linker script to the CPU root directory by Bin Meng · 6 years ago
  14. b28f7b3 riscv: Include bss subsections in linker script by Alexander Graf · 6 years ago
  15. 94a10f2 efi_loader: Rename sections to allow for implicit data by Alexander Graf · 6 years ago
  16. b66af37 riscv: cpu: nx25: Rename as ax25 by Rick Chen · 7 years ago