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git01.mediatek.com / filogic / uboot / 2df8de28c5ecf1d6b6995b65ec12a2d52cf193f9 / drivers / clk / renesas / r8a77970-cpg-mssr.c
  1. 6811b57 clk: renesas: Add R8A77970 SD0H/SD0 clocks for SDHI by Hai Pham · Thu Jan 26 21:06:06 2023 +0100
  2. f6b3202 clk: renesas: Add and enable CPG reset driver by Marek Vasut · Thu Jan 26 21:02:03 2023 +0100
  3. 814217e clk: renesas: Make reset controller modemr register offset configurable by Marek Vasut · Sun Apr 25 21:53:05 2021 +0200
  4. 0e8dcb7 clk: renesas: Synchronize R-Car Gen3 tables with Linux 5.12 by Marek Vasut · Sun Apr 25 21:10:40 2021 +0200
  5. 22f9fc7 clk: renesas: Only ever access documented bits in clock driver teardown by Marek Vasut · Sat Apr 25 14:57:45 2020 +0200
  6. 8a2b47f dm: treewide: Rename auto_alloc_size members to be shorter by Simon Glass · Thu Dec 03 16:55:17 2020 -0700
  7. 4dcacfc common: Drop linux/bitops.h from common header by Simon Glass · Sun May 10 11:40:13 2020 -0600
  8. 10e4779 SPDX: Convert all of our single license tags to Linux Kernel style by Tom Rini · Sun May 06 17:58:06 2018 -0400
  9. 2eb56a1 clk: renesas: Split SMSTPCR and RMSTPCR tables by Marek Vasut · Mon Jan 15 00:58:35 2018 +0100
  10. 7ef12c2 clk: renesas: Pull Gen3 specific bits into separate header by Marek Vasut · Mon Jan 08 17:09:45 2018 +0100
  11. 28f9004 clk: renesas: Make PLL configurations per-SoC by Marek Vasut · Tue Jan 16 19:23:17 2018 +0100
  12. b923419 clk: renesas: Make clk_ids per-driver by Marek Vasut · Mon Jan 08 16:05:28 2018 +0100
  13. 4eb4e6e clk: renesas: Split RCar Gen3 driver by Marek Vasut · Mon Jan 08 14:01:40 2018 +0100