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git01.mediatek.com / filogic / uboot / 2b8bd9105e4878faec446667ba3c2aa459a7bc3c / include / common_timing_params.h
  1. 2896cb7 driver/ddr/fsl: Add DDR4 support to Freescale DDR driver by York Sun · Thu Mar 27 17:54:47 2014 -0700
  2. f062659 Driver/DDR: Moving Freescale DDR driver to a common driver by York Sun · Mon Sep 30 09:22:09 2013 -0700[Renamed from arch/powerpc/cpu/mpc8xxx/ddr/common_timing_params.h]
  3. 0b81093 mpc8xxx: set x2 DDR3 refresh rate if SPD config requires it by Valentin Longchamp · Fri Oct 18 11:47:20 2013 +0200
  4. 4a71741 powerpc: Fix CamelCase warnings in DDR related code by Priyanka Jain · Wed Sep 25 10:41:19 2013 +0530
  5. de87932 powerpc/8xxx: Enable DDR3 RDIMM support by york · Fri Jul 02 22:25:55 2010 +0000
  6. 88fbf93 Move arch/ppc to arch/powerpc by Stefan Roese · Thu Apr 15 16:07:28 2010 +0200[Renamed from arch/ppc/cpu/mpc8xxx/ddr/common_timing_params.h]
  7. 29514c7 ppc: Move cpu/$CPU to arch/ppc/cpu/$CPU by Peter Tyser · Mon Apr 12 22:28:09 2010 -0500[Renamed from cpu/mpc8xxx/ddr/common_timing_params.h]
  8. 124b082 FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code. by Kumar Gala · Tue Aug 26 15:01:29 2008 -0500