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git01.mediatek.com / filogic / uboot / 2acf84869b2aba691b108fac92f1c6a7abb4c421 / arch / powerpc / cpu / mpc8xxx / ddr / main.c
  1. 9b9372f powerpc/mpc8xxx: Fix DDR SPD failed message by York Sun · Mon Oct 08 07:44:28 2012 +0000
  2. 016095d powerpc/mpc8xxx: Fix DDR initialization waiting for D_INIT by York Sun · Mon Oct 08 07:44:24 2012 +0000
  3. 11dd884 powerpc/mpc8xxx DDR: Fall back to raw timing for first controller only by York Sun · Fri Aug 17 08:22:42 2012 +0000
  4. e8dc17b powerpc/mpc8xxx: Enable 3-way and 4-way DDR interleaving by York Sun · Fri Aug 17 08:22:39 2012 +0000
  5. 2400904 powerpc/ddr: fix fsl_ddr_get_dimm_params compile error by Shaohui Xie · Thu Jun 28 23:36:38 2012 +0000
  6. bd495cf powerpc/8xxx: Add support for interactive DDR programming interface by York Sun · Fri Sep 16 13:21:35 2011 -0700
  7. 92b46ac powerpc/mpc8xxx: Add SPD EEPROM address for single controller 2 slots by York Sun · Fri Aug 26 11:32:41 2011 -0700
  8. 09d8aa8 powerpc/mpc8xxx: Adding fallback to raw timing on supported boards by York Sun · Tue Jun 07 09:42:17 2011 +0800
  9. e73cc04 powerpc/mpc8xxx: Enable calculation for fixed DDR chips by York Sun · Tue Jun 07 09:42:16 2011 +0800
  10. dd803dd powerpc/mpc8xxx: Add 16-bit support for DDR3 by York Sun · Fri May 27 07:25:51 2011 +0800
  11. c68e86c powerpc/8xxx: Refactor fsl_ddr_get_spd into common code from board by Kumar Gala · Mon Jan 31 22:18:47 2011 -0600
  12. 80ad401 8xxx/ddr: add support to only compute the ddr sdram size by Haiying Wang · Wed Dec 01 10:35:31 2010 -0500
  13. 2d8ecac MPC8xxx DDR: align informational prints by Becky Bruce · Fri Dec 17 17:17:59 2010 -0600
  14. 93799ca powerpc/8xxx: Fix bug in memctrl interleaving & bank interleaving on cs0~cs4 by york · Fri Jul 02 22:25:52 2010 +0000
  15. 88fbf93 Move arch/ppc to arch/powerpc by Stefan Roese · Thu Apr 15 16:07:28 2010 +0200[Renamed from arch/ppc/cpu/mpc8xxx/ddr/main.c]
  16. 29514c7 ppc: Move cpu/$CPU to arch/ppc/cpu/$CPU by Peter Tyser · Mon Apr 12 22:28:09 2010 -0500[Renamed from cpu/mpc8xxx/ddr/main.c]
  17. f4018f9 85xx, 86xx: Add common board_add_ram_info() by Peter Tyser · Fri Jul 17 10:14:48 2009 -0500
  18. 68ef4bd fsl-ddr: Fix handling of >4G of memory when !CONFIG_PHYS_64BIT by Kumar Gala · Thu Jun 11 23:42:35 2009 -0500
  19. 45eea1d fsl-ddr: Allow system to boot if we have more than 4G of memory by Kumar Gala · Tue Feb 10 23:53:40 2009 -0600
  20. b135d93 fsl ddr skip interleaving if not supported. by Ed Swarthout · Wed Oct 29 09:21:44 2008 -0500
  21. b834f92 Check DDR interleaving mode by Haiying Wang · Fri Oct 03 12:37:10 2008 -0400
  22. fa44036 Pass dimm parameters to populate populate controller options by Haiying Wang · Fri Oct 03 12:36:55 2008 -0400
  23. 272b596 Make DDR interleaving mode work correctly by Haiying Wang · Fri Oct 03 12:36:39 2008 -0400
  24. 9dbbd7b Coding style cleanup, update CHANGELOG by Wolfgang Denk · Sat Sep 13 02:23:05 2008 +0200
  25. 124b082 FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code. by Kumar Gala · Tue Aug 26 15:01:29 2008 -0500