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git01.mediatek.com / filogic / uboot / 2a9364b6e8e6747da0b6e7d83d3f3f247bf9ba64 / board / freescale / mpc8641hpcn / ddr.c
  1. 24b66e5 powerpc/mpc85xx: Display a warning for unsupported DDR data rates by York Sun · Mon Jun 27 13:30:55 2011 -0700
  2. c68e86c powerpc/8xxx: Refactor fsl_ddr_get_spd into common code from board by Kumar Gala · Mon Jan 31 22:18:47 2011 -0600
  3. b78c7bf powerpc/8xxx: Replace fsl_ddr_get_mem_data_rate with get_ddr_freq() by Kumar Gala · Mon Jan 31 20:36:02 2011 -0600
  4. a06d74c fsl-ddr: use the 1T timing as default configuration by Dave Liu · Fri Nov 21 16:31:43 2008 +0800
  5. 82f15f3 Coding Style cleanup, update CHANGELOG by Wolfgang Denk · Sun Nov 02 16:14:22 2008 +0100
  6. 4e0dd7f Add DDR options setting on MPC8641HPCN board by Haiying Wang · Fri Oct 03 12:37:57 2008 -0400
  7. fa44036 Pass dimm parameters to populate populate controller options by Haiying Wang · Fri Oct 03 12:36:55 2008 -0400
  8. cad506c FSL DDR: Convert MPC8641HPCN to new DDR code. by Kumar Gala · Tue Aug 26 15:01:35 2008 -0500