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git01.mediatek.com / filogic / uboot / 29e00130854ddcf3ada5dfd63479abbab453b15d / arch / arm / mach-sunxi / dram_sun50i_h616.c
  1. ac8154d sunxi: Add TPR2 parameter for H616 DRAM driver by Jernej Skrabec · Mon Apr 10 10:21:19 2023 +0200
  2. 9ec04b0 sunxi: Parameterize "unknown feature" in H616 DRAM driver by Jernej Skrabec · Mon Apr 10 10:21:17 2023 +0200
  3. 63ab955 sunxi: Parameterize bit delay code in H616 DRAM driver by Jernej Skrabec · Mon Apr 10 10:21:16 2023 +0200
  4. 47e263e sunxi: Make bit delay function in H616 DRAM code void by Jernej Skrabec · Mon Apr 10 10:21:15 2023 +0200
  5. 64712da sunxi: Always configure ODT on H616 DRAM by Jernej Skrabec · Mon Apr 10 10:21:14 2023 +0200
  6. 6a6fe86 sunxi: Convert H616 DRAM options to single setting by Jernej Skrabec · Mon Apr 10 10:21:13 2023 +0200
  7. dd533da sunxi: parameterize H616 DRAM ODT values by Jernej Skrabec · Mon Apr 10 10:21:12 2023 +0200
  8. 5a08848 sunxi: cosmetic: Fix H616 DRAM driver code style by Jernej Skrabec · Mon Apr 10 10:21:11 2023 +0200
  9. 472d404 sunxi: Fix write to H616 DRAM CR register by Jernej Skrabec · Mon Apr 10 10:21:10 2023 +0200
  10. e04cd49 sunxi: prcm: Add a few registers by Jernej Skrabec · Sun Jan 30 15:27:13 2022 +0100
  11. 4e04842 sunxi: Fix H616 DRAM read calibration for dual rank by Jernej Skrabec · Sat Jan 29 16:58:43 2022 +0100
  12. 137ab1c sunxi: fix H616 DRAM ODT support by Jernej Skrabec · Sat Jan 29 16:58:42 2022 +0100
  13. 0f7c8bc sunxi: clock: H6/H616: Fix PLL clock factor encodings by Andre Przywara · Wed May 05 13:53:05 2021 +0100
  14. e4aa24b sunxi: Add H616 DRAM support by Jernej Skrabec · Mon Jan 11 21:11:43 2021 +0100