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git01.mediatek.com / filogic / uboot / 2966cd255572e439003c3a556e08ca75532a38dd / arch / powerpc / cpu / mpc8xxx / ddr / options.c
  1. 59cb44c arch/powerpc/cpu/mpc8xxx/ddr/options.c: Fix GCC 4.6 build warning by Kumar Gala · Wed Nov 09 10:05:21 2011 -0600
  2. 454f507 powerpc/mpc8xxx: Add DDR2 to unified DDR driver by York Sun · Fri Aug 26 11:32:43 2011 -0700
  3. f0345e2 powerpc/mpc8xxx: Move DDR RCW overriding to common code by York Sun · Wed Aug 24 09:40:26 2011 -0700
  4. 3c5ffd4 powerpc/mpc8xxx: fix DDR data width checking by York Sun · Mon Jun 27 13:35:25 2011 -0700
  5. dd803dd powerpc/mpc8xxx: Add 16-bit support for DDR3 by York Sun · Fri May 27 07:25:51 2011 +0800
  6. 5fb9f6f powerpc/mpc8xxx: adjust DDR burst length and chop accroding to sdram width by York Sun · Fri May 27 07:25:48 2011 +0800
  7. ba0c2eb mpc85xx: Enable unique mode registers and dynamic ODT for DDR3 by York Sun · Mon Jan 10 12:03:00 2011 +0000
  8. 0ac71ea mpc8xxx: Enable ECC on/off control in hwconfig by York Sun · Mon Jan 10 12:02:57 2011 +0000
  9. 7230160 powerpc/8xxx: Add hwconfig APIs to address early parsing used by DDR init by Kumar Gala · Sun Jan 09 11:37:00 2011 -0600
  10. f582d98 powerpc/8xxx: Move fsl_is_spd() into generic 8xxx ddr code by Kumar Gala · Sun Jan 09 14:06:28 2011 -0600
  11. 1714e49 powerpc/8xxx: Improvement to DDR parameters by york · Fri Jul 02 22:25:56 2010 +0000
  12. 4260372 powerpc/8xxx: Enabled address hashing for 85xx by york · Fri Jul 02 22:25:54 2010 +0000
  13. f4f93c6 powerpc/8xxx: Enable quad-rank DIMMs. by york · Fri Jul 02 22:25:53 2010 +0000
  14. 93799ca powerpc/8xxx: Fix bug in memctrl interleaving & bank interleaving on cs0~cs4 by york · Fri Jul 02 22:25:52 2010 +0000
  15. 6404209 powerpc/8xxx: Enabled hwconfig for memory interleaving by Kumar Gala · Wed Jul 14 10:04:21 2010 -0500
  16. 88fbf93 Move arch/ppc to arch/powerpc by Stefan Roese · Thu Apr 15 16:07:28 2010 +0200[Renamed from arch/ppc/cpu/mpc8xxx/ddr/options.c]
  17. 29514c7 ppc: Move cpu/$CPU to arch/ppc/cpu/$CPU by Peter Tyser · Mon Apr 12 22:28:09 2010 -0500[Renamed from cpu/mpc8xxx/ddr/options.c]
  18. 707aa5c fsl-ddr: change the default burst mode for DDR3 by Dave Liu · Fri Mar 05 12:22:00 2010 +0800
  19. 64ee7df fsl-ddr: add the override for write leveling by Dave Liu · Wed Dec 16 10:24:37 2009 -0600
  20. 0f9318f fsl-ddr: Fix the chip-select interleaving issue by Dave Liu · Thu Nov 12 07:26:37 2009 +0800
  21. 4be87b2 fsl-ddr: add the DDR3 SPD infrastructure by Dave Liu · Sat Mar 14 12:48:30 2009 +0800
  22. c0f3b3c fsl-ddr: ignore memctl_intlv_ctl setting if only one DDR controller by Kumar Gala · Fri Feb 06 09:56:34 2009 -0600
  23. a06d74c fsl-ddr: use the 1T timing as default configuration by Dave Liu · Fri Nov 21 16:31:43 2008 +0800
  24. b135d93 fsl ddr skip interleaving if not supported. by Ed Swarthout · Wed Oct 29 09:21:44 2008 -0500
  25. b834f92 Check DDR interleaving mode by Haiying Wang · Fri Oct 03 12:37:10 2008 -0400
  26. fa44036 Pass dimm parameters to populate populate controller options by Haiying Wang · Fri Oct 03 12:36:55 2008 -0400
  27. 124b082 FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code. by Kumar Gala · Tue Aug 26 15:01:29 2008 -0500