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git01.mediatek.com / filogic / uboot / 27367b204f3e622833f4049290117b43395872a1 / board / freescale / ls2080ardb / ddr.h
  1. f1510e6 board/freescale: Update ddr clk_adjust by Shengzhou Liu · Wed May 04 10:20:22 2016 +0800
  2. 48f6ab5 armv8/ls2080ardb: Update DDR timing to support more UDIMMs by Shengzhou Liu · Thu Apr 07 14:41:30 2016 +0800
  3. 122bcfd armv8: LS2080A: Rename LS2085A to reflect LS2080A by Prabhakar Kushwaha · Mon Nov 09 16:42:07 2015 +0530[Renamed from board/freescale/ls2085ardb/ddr.h]
  4. e12abcb armv8/ls2085ardb: Add support of LS2085ARDB platform by York Sun · Fri Mar 20 19:28:24 2015 -0700