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git01.mediatek.com / filogic / uboot / 26517afe9113fb6c5331df640c5ca79e859110bd / drivers / watchdog / xilinx_wwdt.c
  1. 4171095 clk: zynq: Add dummy clock enable function by Michal Simek · Tue Feb 09 15:28:15 2021 +0100
  2. 75e534b dm: Avoid accessing seq directly by Simon Glass · Wed Dec 16 21:20:07 2020 -0700
  3. b75b15b dm: treewide: Rename ..._platdata variables to just ..._plat by Simon Glass · Thu Dec 03 16:55:23 2020 -0700
  4. aad29ae dm: treewide: Rename ofdata_to_platdata() to of_to_plat() by Simon Glass · Thu Dec 03 16:55:21 2020 -0700
  5. fa20e93 dm: treewide: Rename dev_get_platdata() to dev_get_plat() by Simon Glass · Thu Dec 03 16:55:20 2020 -0700
  6. 71fa5b4 dm: treewide: Rename 'platdata' variables to just 'plat' by Simon Glass · Thu Dec 03 16:55:18 2020 -0700
  7. 8a2b47f dm: treewide: Rename auto_alloc_size members to be shorter by Simon Glass · Thu Dec 03 16:55:17 2020 -0700
  8. f4aecf4 watchdog: versal: Add support for Xilinx window watchdog by Ashok Reddy Soma · Wed Mar 11 03:06:04 2020 -0600