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git01.mediatek.com / filogic / uboot / 23aee9fccb0a828847cd767a505902189b7e4701 / drivers / clk / clk_rk3288.c
  1. 94906e4 rockchip: spl: Support full-speed CPU in SPL by Simon Glass · Thu Jan 21 19:45:17 2016 -0700
  2. e6a682b rockchip: rk3288: clock: Fix various minor errors by Simon Glass · Thu Jan 21 19:45:15 2016 -0700
  3. 273afb2 rockchip: clk: Add support for clocks needed by the displays by Simon Glass · Thu Jan 21 19:45:02 2016 -0700
  4. 5562bf1 rockchip: Rename the CRU_MODE_CON fields by Simon Glass · Thu Jan 21 19:45:01 2016 -0700
  5. 410d45c rockchip: clk: Make rkclk_get_clk() SoC-specific by Simon Glass · Thu Jan 21 19:44:05 2016 -0700
  6. d4a8a68 rockchip: mmc: Update the driver to use the new clock ID by Simon Glass · Thu Jan 21 19:43:45 2016 -0700
  7. 344f366 rockchip: clock: Add a function to find a clock by ID by Simon Glass · Thu Jan 21 19:43:41 2016 -0700
  8. 398ced1 rockchip: clk: Add a function to get a peripheral clock rate by Simon Glass · Thu Jan 21 19:43:40 2016 -0700
  9. afe0cb0 rockchip: clock: Rename the general clock variable to gclk_rate by Simon Glass · Thu Jan 21 19:43:39 2016 -0700
  10. 8d32f4b rockchip: Use a separate clock ID for clocks by Simon Glass · Thu Jan 21 19:43:38 2016 -0700
  11. ecf20f6 clk: add static qualifier to local functions by Masahiro Yamada · Wed Jan 13 13:16:10 2016 +0900
  12. 421358c rockchip: rk3288: Add clock driver by Simon Glass · Sun Aug 30 16:55:31 2015 -0600